Synthesis Procedure for Fully-Testable Non-Scan Finite-State Machine

Synthesis Procedure for Fully-Testable Non-Scan Finite-State Machine

m Partition NSL into single-cone circuits

m Single stuck-fault Þ correct & incorrect next-state differ by exactly one bit.

m Perform state assignment such that all states differing in one bit assert different outputs Þ one-step propagation

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