Presentation of the 2005 Phil Kaufman Award to
Phil Moorby

1st November, 2005
A. Richard Newton

Ladies and gentlemen it is again an honor for me to present the 2005 Phil Kaufman Award. We are here tonight to recognize the many technical accomplishments to the EDA industry of the 12^th Phil Kaufman award winner, Phil Moorby, but especially his efforts in the development of the Verilog language and its associated family of simulators.  As his former research advisor and former boss Professor Gerry Musgrave summed it up, “I’m delighted that Phil has won this award. He has reproduced major success at least three times in his EDA career, and this award is testimony to his very significant technical and linguistic capabilities.”

Phil was born in Birmingham, England—hence the accent—and completed his undergraduate and graduate degrees in Southampton and Manchester respectively, majoring in mathematics and computer science.

It was in 1976 that Phil joined Professor Gerry Musgrave’s group at Brunel University as a Research Fellow, to undertake PhD research in timing analysis.  Now I have to back up a little. We senior members of the EDA community certainly remember that talented, young, very energetic lecturer from Bradford University in England who launched the development of the HILO simulator and then moved his research team to Brunel.  In those days Brunel, along with Edinburgh and Imperial College, was one of the leading CAD research universities in England. In fact, other than his physical age, Professor Gerry Musgrave really hasn’t changed much at all in the intervening thirty years!  Phil cut his EDA teeth on HILO and two years after joining Gerry at Brunel he put his PhD research on the shelf for a while (forever?) and joined the HILO-2 team as a core architect and developer.  Along with Peter Flake—who Phil considers a technical mentor, Simon Davidmann, and half a dozen others, they developed HILO-2 for the Ministry of Defense in England, primarily as a board-level test simulator to generate and validate tests.  But of course, HILO evolved to become an RTL language and environment, with a lot of help from Phil.  As Simon recalls, “Phil worked primarily on the HILO kernel, was responsible for the key scheduler internals and then the fault simulator, where he invented some clever new algorithms for parallel fault simulation that made HILO a strong, industrial-grade, high performance fault simulator.”

Now along the way, one of HILO's first US-based customers was a young and very accomplished engineer from IBM and later Wang—a guy named Dr. Prabhu Goel who was working at Wang in Lowell, Massachusetts back in 1982.  HILO was a board level simulator in those days, but Prabhu had other ideas and tried to use it to simulate an 8,000 gate chip he was developing—what became later  known as an ASIC—and was very impressed with the results. Prabhu was a simulation and test expert himself and had invented the very important Path Oriented Decision Making (PODEM) algorithm for test generation that is still in widespread use today. More importantly, as an excellent judge of talent, Phil Moorby caught Prabhu’s eye. So it wasn’t too unlikely that when he left Wang a year later and founded Automated Integrated Design Systems (AIDS), soon to be renamed to Gateway Design Automation for obvious reasons, that he invited Phil to join him in the US.  Phil’s Uxbridge, England backyard view of a large, ugly ‘gasometer’ (a storage tank for home heating gas) was soon replaced by the beautiful fall colors of his view from a room above Prabhu’s garage in West Acton, Massachusetts.

So what then became of HILO? It was around that time that the HILO team hooked up with ICL, Cirrus Computer, and then the tester company GenRad in England to develop HILO-3.  “GenRad wasn’t interested in RTL simulation or ASICs—they wanted to sell more testers and they saw HILO as a way of doing that,” says Gerry Musgrave.  In the mean time, Gateway caught the ASIC wave and took off.

When Gateway started, it wasn’t entirely clear where they were headed. Simulation? Tools for test? Timing analysis? Another Gateway co-founder was Chi-lai Huang, who had just completed his PhD in the hot new area of logic synthesis. Would Gateway become a synthesis company, perhaps?  So no wonder when Phil put his mind to designing the new language for what eventually became Verilog, he and the team considered its implications for synthesis as well as for fast simulation. “No matter where we were headed, we needed a new language and a new simulator,” says Phil, “and that was the start of Verilog.”  In 1985, twenty years ago this year and about one year after he began working on it, Phil had the first version of Verilog running in the lab.

Gateway was the first company of its type to recognize the importance of the ASIC revolution. “Prabhu saw that vision very early on,” says Phil. “Business-wise, it was all Prabhu.” In fact, Prabhu was awarded the IEEE Industrial Pioneer Award in 2003 for his many contributions, an award that honors outstanding scientists and engineers who successfully translate research into commercial products or applications.  At the same time as the ASIC industry was emerging, it looked like hardware accelerators might take over the simulation business—ZyCAD especially, but there were also important efforts at Daisy Systems and internal to major computer companies.  But the MOS-based ASIC industry mandated a need to deal with switches—bidirectional gates—and to handle ‘very large circuits’; as many as 50,000 logic gates! “A HILO netlist is almost identical to Verilog,” says Peter Flake. “But the behavioral level is very different—Phil designed it to be more like a programming language, where every assignment happened immediately. This is one place where Verilog got its speed.”

Verilog was really a mixed-level simulator, handling switches, gates, and the register level as well. But the emphasis was always speed.  Phil is most proud of his Verilog-XL algorithms, written in assembler and ‘optimizing the heck out of it,’ as he says.  Developing efficient algorithms and their implementation has always been a real craft—an holistic endeavor where instruction sequencing, managing storage and data movement, all in the context of a particular set of tradeoffs on a particular class of computers, are all keys to success.  It is a lot more than mathematics—it is all about engineering as well.  Although Verilog-XL was about half the speed of the ZyCAD hardware accelerator, it was a lot less expensive and a lot easier to use—along with the ASIC industry, it took off!

And then we entered the ‘language dark years’ and time of the ‘HDL Wars,’ pitting VHDL against Verilog, and a small cadre of bit players.  Cadence acquired Gateway, making Phil Moorby the first Corporate Fellow at Cadence Design Systems, and then Cadence opened up the Verilog language, leading to the ‘synthesizeable subset’ skirmishes.  The Number 10 employee at Gateway, Craig Robbins told me, “When I first met Phil I thought he was just one of the developers. As we grew, lots of people got rattled for lots of reasons. But Phil never got rattled. He just knew we would win! He was almost a father figure to many of us—unassuming and always positive.”

When we emerged into the light of a new century, it was clear who the winner was.  As Joe Costello was quoted as saying even back in 1995, "...Adoption of VHDL was one of the biggest mistakes in the history of design automation, causing users and EDA vendors to waste hundreds of millions of dollars..." I’ll leave you to judge that one, but according to John Cooley’s DeepChip, in 2005 around 60% of designers used Verilog alone on their designs, while just 3% used VHDL and the rest used a combination of Verilog and VHDL. Now that is market dominance! That is impact!

Fellow Kaufmann Award winner and Cadence Director Alberto Sangiovanni-Vincentelli sums it up this way: “Verilog was always more pragmatic than VHDL and as such was more applicable for synthesis—which further accelerated its wide adoption.” It was pragmatic by design.

Phil left Cadence around 1992 and even left EDA for while, working on video editing at Avid and hooking up with a couple of unsuccessful startups, before returning to join his old HILO buddies Simon Davidmann and Peter Flake who had founded Co-Design to extend Verilog into SUPERLOG (now known as SystemVerilog by the IEEE). They were already off and running when Phil joined. Peter told me, “In Co-Design, our idea was to unify hardware, software, design architecture, and the testbench space. SUPERLOG could do all four, but in the end the real benefit was unifying the design and the testbench.” Phil started out on the Co-Design technical advisory board, but later decided to join the company full time, where he began by developing the System-C interface to the product and working on the compiled-code simulation capability. As Simon commented, “Phil is one of the most fantastic deep thinkers there is, as well as one of the best software engineers I have ever met. I recall when we were adding things to Verilog, Phil would always say ‘For everything you add, try to take two away—keep it simpler!’”  Co-Design Automation was acquired by Synopsys in 2002 and Phil found himself again working for one of the Big Three.

In addition to his all-round contribution to the SystemVerilog language, including consistency with the Verilog standard, Phil paid special attention to the scheduling semantics of the language.  I won’t go into the technical details, but the scheduling semantics are quite challenging and complex in SystemVerilog because of the co-existence of design description, testbench, and assertions in the same environment and because of their dynamic interaction. Phil developed an innovative solution by defining their interaction semantics precisely and by demonstrating it through his VCS implementation.

According to Manoj Ghandi at Synopsys, “The reason this is very important for the industry is that as we make substantial additions to the Verilog language in SystemVerilog, we must make sure the investment the industry has made in Verilog over the past 20 years is preserved and the new semantics are well designed for the industry to take Verilog to next level.”  That has been Phil’s main job.

So what lesson does Phil offer us, based on his many successes over the years?  The other day he told me quietly, “First and foremost, you have to develop a killer-app and dominate a segment technically. In the Verilog case, that was fast gate-level simulation.  Then you need a strategic advantage, and for us that was the impending synergy between RTL simulation and synthesis.”  Phil, you said it! You did it.

From the perspective of Viewlogic founder and former CEO Alain Hannover: “Phil’s work revolutionized hardware design with the introduction of Verilog, which has become the gold standard for digital simulation in the industry. It has had as much impact on hardware design as the ‘C’-language had on software development in the 1970’s.”

All this impact, quietly and in the background of a fast-moving industry.  Synopsys CEO Aart De Geus put it like this: “In every field there are a few individuals that quietly make a huge difference. They are the true experts and often they are only recognized by other true experts. … Phil is such a person. His impact in our field cannot be overestimated. Quiet guy maybe, but wow, what impact!” Gerry Musgrave added: “Still waters run deep!” That’s Phil.

Ladies and gentlemen, the 12^th Phil Kaufman Award Winner, Phil Moorby!