Design Specification and Verification
Design Specification and Verification
m Systems are growing more complex faster than specification and verification tools can improve.
Ô The gap is widening rapidlyÔ Issue is "Is what I said what I want?" more than "Is what I said what I got?"
m Major problem is unambiguous, design-oriented specification of a system.
Ô VHDL is not the answer! We need a Policy-of-Use for VHDL: (subset of constructs) + (collection of library routines)
m Verification task will require more than fast, uniprocessor-based simulators.
Ô Proof-based formal verification will probably not be the answer. More likely multiprocessor-based (massively parallel?) "cube-simulation"-oriented approach will be most useful.