Synthesis-Directed Sequential Test
Synthesis-Directed Sequential Test
m Increasing importance with synthesis & multiple vendors
Ô Short term: automatic, scan-based approachesÔ Longer term: "synthesis supported" test strategies
m Examples:
g After state-assignment and logic optimization, determine latches which must be scan permit testing or to bound test-pattern size (partial scan)g During state-assignment and logic optimization, add logic as needed to make circuit fully-testable from its primary inputs (non-scan)