Application of Logic Synthesis
Application of Logic Synthesis
m Area and Timing Optimization
Ô Meet performance requirements is major goal Ô Automatic generation of schematics essential
m Technology Mapping
Ô Map logic to multiple vendor libraries for comparison Ô Map existing logic to multiple technologies (e.g. Gate array to standard cell, CMOS to ECL).
m Next Generation: Automation of both combinational and sequential testing issues.