Synthesis Procedure for Fully-TestableNon-Scan Finite-State Machine (Devadas, et.al. 1988)

Latches

Output Logic

Primary

Inputs

(PIs)

Primary

Outputs

(POs)

1

2

N

NSL

• Partition NSL into single-cone circuits

• Single stuck-fault Þ correct & incorrect next-state differ by exactly one bit.

• Perform state assignment such that all states differing in one bit assert different outputs Þ one-step propagation

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