Niraj Shah
EE290a - Homework 2
 

IP Search - PCI Bus Core

For this homework, I researched many different implementations of PCI bus cores. PCI bus cores make it possible to implement a complete PCI interface, as opposed to PCI bridges or targets, which are only part of the interface. For the sake of brevity, I will examine the following five representative designs:
  1. PCI Synthesizable Core by Sand Microelectronics, Inc.
  2. The PCI-66 FlexCore Architecture by LSI Logic Corporation
  3. Design Ware DWPCI Macrocell by Synopsys Corporate
  4. PCI - Local Bus Interface Macrocell by Lucent Technologies, Inc.
  5. PCI Core by ASIC Designers, Inc.
All of these cores were found from the Design & Reuse IP Selector, a virtual library of IP blocks that allows you to compare different implementations and provides pointers to IP companies. The above cores fall under the taxonomy of  Bus Interfaces => PCI (Peripheral Controller Interface) => Device.

Description

Core 1 - PCI Synthesizable Core by Sand Microelectronics, Inc.

The PCI Synthesizable Core is fully compliant with Revision 2.1 of the PCI specification. The core can be configured 16 different ways. The type of clock scheme for the PCI and FIFO bus can be asynchronous or synchronous. The widths of of each of the following busses can configured to be either 32 or 64 bits: the PCI bus, the Master FIFO bus, and the Slave FIFO bus. The FIFOs are programmable read/write FIFOs that can either be implemented using flip-flops or pre-placed RAM. The core can be customized and configured error-free via Sand's RapidScript tool. Additionally, it is possible to upgrade from 32 bit PCI to 64 bit PCI without changing the application since the application side interface is the same for both flavors of PCI. All of this information can be found in [1].
This core offers a great deal of design of flexibility, which would be ideal if you were in need of a wide variety of PCI bus implementations, for example. Since it is delivered as a soft block, the user has a lot of latitude in the core's final realization (e.g. it can be mapped to an FPGA). A limitation of this core is that does not operate at 66 MHz.

Core 2 - The PCI-66 FlexCore Architecture by LSI Logic Corporation

The PCI-66 FlexCore Architecture is Revision 2.1 compliant. It is composed of the following blocks: Slave, Master, FIFO controller, FIFO Memory, and Configuration Space. This architecture allows three different configurations of controller interfaces:  Slave, Slave/Master, and Slave/Master/FIFO. The core supports application interfaces widths of 32 or 64 bits. These options make it possible to tailor the core to a variety of systems. The FIFO memory blocks are configurable and composed of compiled RAM structures. This description is taken from [3]. This core also has built-in testability and test vectors that provide 99% fault coverage are provided [6].
This core is much more limiting that first one. Since it a hard macro, it is only useful if LSI is fabricating your chip. The flip side is that the core is already verified and can easily be integrated with other LSI cores.

Core 3 - Design Ware DWPCI Macrocell by Synopsys Corporate

The DWPCI Macrocell is PCI 2.2 compliant and can be configured for 32 or 64 bit PCI bus width and FIFO bus width. In addition the PCI clock can range from 0-33 MHz or 66 MHz. However, the core does not support asynchronous PCI clock schemes. This core comes with an extensive user interface package that aids the designer through installation, configuration, and synthesis of the core. According to their documentation, it takes only 3 weeks for a designer to create a PCI design using this core. With the core, a verification suite is included that includes functional models, a compliance suite, and protocol checkers. Also included in the core is full scan logic. (description from [7])
The major advantage of this core seems to be its ease of configurability through its user interface. In addition, it is the only core I found that is Revision 2.2 compliant. Testing and verification are also made easier by various features. This core is a little limiting in that it does not support asynchronous PCI, but I'm sure how much of a factor that is.

Core 4 - PCI Local Bus Interface Macrocell by Lucent Technologies, Inc.

The PCI Local Bus Interface Macrocell is fully compliant with Revision 2.1 and is functionally equivalent to Sand Microelectronic's PCI core (Core 1). It is not clear why Lucent's data sheet [8] states this as a feature. The only difference between Lucent's core and Sand Microelectronic's core is that Lucent's implementation is 2k gates cheaper and is delivered as a firm macro [9]. In addition, this core uses preverified models using Verilog source code.

Core 5 - PCI Core by ASIC Designers, Inc.

This core is PCI Revision 2.1 compliant, but also supports the power management features of PCI 2.2. It supports 32 bit and 64 bit PCI bus widths and can operate at speeds up to 66 MHz. The host bus can operate up to 100 MHz. The modular design of the core makes is customizable to a variety of applications. The core is optimized for host bridging and adapter applications in the areas of networking, graphics, and disk access. In addition, the core is fully observable through the local register bus and has full scan logic. All of this information can be found in [10].
This core also seems to have an easy to use UI that makes configuring the core relatively simple. However, details of this were not available. Integrating this core seems easier because it is deadlock-free by design.

Performance

Core 1 - PCI Synthesizable Core by Sand Microelectronics, Inc.

Zero wait state read and write burst are supported for a maximum performance of 132 Mbytes/sec transfer rate. The critical path for the core is 11 levels of logic [2]. Though it does not mention the bus speed, it can be inferred from [2] that this core only supports speeds up to 33 MHz.

Core 2 - The PCI-66 FlexCore Architecture by LSI Logic Corporation

This core supports synchronous operation up to 33 MHz and 66MHz. Asynchronous operation up to 100 MHz is possible. No other information was available.

Core 3 - Design Ware DWPCI Macrocell by Synopsys Corporate

This core can operate from 0-33 MHz and 66 MHz. To provide greater performance, zero-wait-state data transfers are implemented. With a 64-bit bus width, the core has a burst transfer rate of 264 Mbytes/sec at 33 MHz and 528 Mbytes/sec at 66 MHz.

Core 4 - PCI Local Bus Interface Macrocell by Lucent Technologies, Inc.

Since this core is functionally equivalent to core 1, the maximum performance is a transfer rate of 132 Mbytes/sec.

Core 5 - PCI Core by ASIC Designers, Inc.

The product sheet for this core does not provide any specific performance information.
 

Power

Core 1 - PCI Synthesizable Core by Sand Microelectronics, Inc.

No power information was available.

Core 2 - The PCI-66 FlexCore Architecture by LSI Logic Corporation

Since this core is delivered as a hard macro, the power information depends on the technology it is implemented in. The only power-related information available was that the core is available in technologies that can operate at 3.3V, 2.5V, or 1.8V [5]. In addition, the core can interface with 3.3V or 5V bus environments [3].

Core 3 - Design Ware DWPCI Macrocell by Synopsys Corporate

No power information was available.

Core 4 - PCI - Local Bus Interface Macrocell by Lucent Technologies, Inc.

No power information was available.

Core 5 - PCI Core by ASIC Designers, Inc.

No power information was available.
 

Cost

Core 1 - PCI Synthesizable Core by Sand Microelectronics, Inc.

For a 1 level deep FIFO, the gate count for the core is approximately 10k [2].

Core 2 - The PCI-66 FlexCore Architecture by LSI Logic Corporation

No cost information was available.

Core 3 - Design Ware DWPCI Macrocell by Synopsys Corporate

No cost information was available.

Core 4 - PCI - Local Bus Interface Macrocell by Lucent Technologies, Inc.

For a 1 level deep FIFO, the gate count for the core is approximately 8k [8].

Core 5 - PCI Core by ASIC Designers, Inc.

No cost information was given, though they claim the core has "one of the smallest gate counts of all cores available today" [10].
 

Use Model

Core 1 - PCI Synthesizable Core by Sand Microelectronics, Inc.

The core is available in Verilog or VHDL. This core has been implemented on an ASIC and an FPGA. Though the PCI Core FAQ claims the setup and output timings are difficult to meet in an FPGA implementation [2].

Core 2 - The PCI-66 FlexCore Architecture by LSI Logic Corporation

This macro is only available hard in LSI's G10 and G11 ASIC technology [4]. This means the macro is available in 0.25u and 0.18u [5].

Core 3 - Design Ware DWPCI Macrocell by Synopsys Corporate

The core is available in Verilog or VHDL [7].

Core 4 - PCI - Local Bus Interface Macrocell by Lucent Technologies, Inc.

Though this macro is functionally equivalent to core 1, it is delivered as a firm (gate-level netlist) macro [9].

Core 5 - PCI Core by ASIC Designers, Inc.

The core is available as a soft (Verilog or VHDL) or firm (gate-level netlist) macro [10].
 

References

[1] Sand Microelectronic's Product Web Page for the PCI core
[2] Sand Microelectronic's FAQ for the PCI core
[3] LSI Logic's PCI-66 FlexCore Architecture
[4] CoreWare Availability
[5] LSI Logic's ASIC Technology
[6] LSI Logic's CoreWare Program
[7]  Synopsys DesignWare DWPCI MacroCell -- Datasheet
[8] Lucent's PCI Local Bus Interface Macrocell Advance Data Sheet
[9]  Design & Reuse's Entry for Lucent's PCI core
[10] ASIC Designers Inc. PCI Core Product Sheet