EE290A HW2

Microcontroller Survey

Philip Chong

1. Motorola 68HC11

The Motorola 68HC11 is one of the most well-known microcontrollers on today's market. Its high degree of integration makes it very attractive to designers; the basic 'A' series of the 68HC11 incorporates RAM and ROM, flexible serial and parallel interfaces, timers and interrupt generators, and a multiple channel A/D converter all on the same piece of silicon. Other models in the family add additional components (such as pulse-width modulators or EEPROM) and/or give the designer more of the aforementioned resources. For all their integration, these parts are very low-priced, about $10 in single quantities.

The downside of the HC11 is its speed. indicates the basic model is capable of only running up to 3MHz. The instruction clock runs at 1/4 the speed of the main clock, and a quick glance at the instruction set shows that most instructions take roughly 4 instruction clock cycles to complete. As the design is not pipelined, this means an effective instruction rate of about 190k instructions/second. Exacerbating this low throughput is the register-poor architecture (there is only a single accumulator, plus a few auxilliary registers for indexing, etc.) as well as the narrow 8-bit path to memory (although internally the accumlator is 16-bits wide).

Power consumption is given from the data sheets to be 27mA (at 5V, this is 135mW) on average; for 0.19 MIPS, this gives 0.0014 MIPS/mW. Note that this metric may not be directly useful in the microcontroller arena, given that microcontrollers often have widely varying data path widths.

References

  1. MC68HC11A8 Technical Data Book, Link
  2. Motorola North America's Price Guide October 1998, Link
  3. Arrow Electronics,, Link

2. Motorola Coldfire

The Coldfire series of microcontrollers represent Motorola's high-end embedded controller line. These products span a very wide range of process technologies and levels of integration. Coldfire has been implemented in technologies ranging from 0.8um to 0.35um; performance ranges from 13.5 MIPS to 70 MIPS (under the Dhrystone benchmark), the latter acheived at 90MHz clock speed. The high-end devices include a MAC unit, which only require a single cycle for an instruction issue, but has a throughput of 3 cycles per instruction (presumably the main integer unit can be used during the MAC execution). The Coldfire core is a full 32-bit RISC CPU, although the instruction and register set are nearly identical to the more familiar 68k. This probably means that code density will be greater than that of traditional RISC CPUs (i.e. the Coldfire will use fewer instructions to acheive the same functionality). This does not directly translate into better performance, however. With few registers (only 8 general-purpose data registers and 8 addressing registers), more accesses to memory will be required in general; furthermore, the use of the CISC-like addressing modes incurs a one or two cycle penalty per instruction. Contrasting the benefits of code size under the CISC-like instruction set and the performance degradation will certainly be dependent on both the target code and the efficiency of the compiler used.

If we assume an average of 2 cycles per instruction, then we will have a throughput of 45 MIPS on the high-end Coldfire devices; this does not account for cache misses (the other Motorola part, 68HC11, does not utilize a cache, while the different models of Coldfire have cache sizes from 512 bytes to 8k). The data sheets give a typical power consumption of 950mW for the top Coldfire device, thus giving us an estimated 0.474 MIPS/mW performance.

Costs for the low-end Coldfire ranged from $25-$45 for single units. Die size information for Coldfire was unavailable.

References

  1. Motorola Coldfire Product Information, Link
  2. Motorola Coldfire Device Chart, Link
  3. Coldfire Programmers Reference Manual, Link
  4. Arrow Electronics,, Link

3. Hitachi SH-2

The Hitachi SH-2 microcontroller features a 32-bit RISC CPU, running at a maximum of 28MHz. Most instructions execute in a single cycle, and there is a MAC unit which can perform one operation in 2-4 cycles. The implementation is in the traditional RISC style, with 16 general-purpose registers, and a 1k I-cache and 2k D-cache.

Typical power consumption is 160mA (800mW) at 28MHz. Assuming a single instruction per cycle, we have 0.035 MIPS/mW. Single unit pricing is about $45 per unit.

References

  1. SH7040 Product Brief, Link
  2. Hamilton-Hallmark: Pricing and Availability, Link

4. General References

  1. CPU Info Center High-Performance Embedded Microprocessor Info, Link
pchong@eecs.berkeley.edu
Feb 09 1999