Moral of the Story
Each process generation will
- Make it twice as easy to realize a fixed (e.g. 66MHz.) timing spec
- Make it twice as easy to realize a fixed (e.g. 100 mm) area requirement
- Make time-to-market requirements 20% more stringent
Time is always on the side of more productive EDA tools/methodologies, but current high-productivity synthesis methodologies are still not meeting QOR requirements