Table of Contents
Viterbi Algorithm
VA : Overview
Viterbi Decoders in digital communication systems
Convolutional Coder and Trellis diagram
ACS recursion for M = 2
Viterbi Decoder block diagram
Path trajectories for the VA at an intermediate trellis step k
Path trajectories for acquisition
Quantization Issues
Characteristic of a 2-bit step-at-zero quantizer
Architecture
Node parallel ACS architecture
PPT Slide
Butterfly trellis structure and resource sharing for the K = 3, rate 1/2 code
Survivor Memory Unit
REA hardware architecture
Decoded Sequence: 0 0 ... 0 1 0
|