SPA Viterbi IP

Software for ADSP-21xx series DSP (~100 mW, 0.35um)

� bps on a 66 MIPS processor

Standard constraint length k = 7

Rates supported: 1/2, 3/4, 7/8, 1/3

13 bit branch metrics, 16 bit state metrics

Code size: 100800 bits

Data memory: 121600 bits

Industry standard FEC algorithms

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