Design: How are Components Described and How are They Modeled?
At lower levels of abstraction:
- Register Transfer Level (RTL): VHDL, Verilog
- Gate Level: Vendor gate library (NAND, flip-flop, etc.)- schematic
- Physical: Mask layout (rectangles on layers)
Ways of delivering SOC IP:
- Hard: Detailed and fully-characterized layout in a specific process
- Soft: RTL Level in Verilog or VHDL; “implementation independent”
- Firm: Soft + a collection of constraints and requirements for the implementation