Summary of status on static verification
Gate-level simulation is a computational bottleneck in implementation verification
Replacing gate-level simulation requires
- Functional verification: Formal implementation verification/equivalence checking
- Timing verification: Static timing verification
Using static timing verification requires handling
- Asynchronous sub-circuits
- False paths
Efficiently eliminating false paths requires
- Path delay modeling - Floating mode/Chen-Du conditions
- Efficient computation:
- Reduction of true delay computation to testing a multifault
- Handling sets of paths