Approach of Static Timing Verification

clk

Combinational

logic

clk

Combinational

logic

• computing longest path delay
  • full path enumeration - potentially exponential
  • longest path algorithm on DAG (Kirkpatrick 1966, IBM JRD) (O(v+e) or O(g + p))

• Currently in successful application on even the largest (ɭM gate) circuits

• has two challenges:
  • asynchronous sub-circuits - limited gate-level simulation
  • false paths - ubiquitous and problematic

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