EE219A: Computer Analysis of Electrical Circuits Outline Lecture 11.2

11/4/98


Click here to start


Table of Contents

EE219A: Computer Analysis of Electrical Circuits Outline Lecture 11.2

Chip Interconnect Systems

Rent’s Rule

Rent’s Rule

Rent’s Curves for Chips & Systems

Average Interconnection Length

Interconnect Effects

Transition Times

Propagation Delay

Interconnect Modeling

Resistance Basics

Resistance Scaling

Resistance Scaling

Capacitance Basics

Plate Capacitance

Edge Capacitance

Capacitance Scaling

Capacitance Scaling

Scaling Summary

PPT Slide

Crosstalk

Lumped Interconnect Model

Evaluation of Lumped RC Interconnect Models

Distributed Model

Inertial & Transmission-Line Delays

Pulse Propagation

Modeling Distributed RC Nets

Coupling Capacitance

The Elmore Time Constant

The Elmore Time Constant

Calculating Elmore Delay

Elmore Delay: Limitations and Extensions

Penfield-Rubenstein Model

Penfield-Rubenstein Bounds

Penfield-Rubenstein

Penfield-Rubenstein Model

Asymptotic Waveform Evaluation (AWE) (Pillage & Rohrer, TCAD April 1990)

Resistor-Transistor Inverter

CMOS Inverter

Effect of Input and Output Time Constants

Computing Path Delays in Networks

Static Timing Analysis

Purpose of Static Timing Verification

Elements of Timing Verification

Elements of Static Timing Verification

Elements of Static Timing Verification

Typical Simplifications

Approach -reduce to combinational

Each combinational block

Problem Formulation

Problem Formulation

Problem Formulation

Algorithm Execution

Algorithm Execution

Algorithm Execution

Algorithm Execution

Algorithm Execution

Algorithm Execution

Algorithm Execution

Algorithm Execution

Algorithm Execution

Algorithm Execution

Algorithm Execution

Critical Path (sub-graph)

Approach of Static Timing Verification

Interesting Example: Carry Bypass Adder

Inside Carry Bypass Adder - 1

Inside Carry Bypass Adder - 2

Capturing Functional Behavior in Analysis

Issues Treated as Orthogonal

Floating Mode Path Delay Assumptions

Single vector condition:Static Sensitization

Example of static sensitization

Lack of static sensitization

Inadequacy of static sensitization

Necessary Condition for Truth of a Path

The World of Paths

Best News: Runtimes

Summary of status on static verification

Author: Richard Newton

Email: rnewton@ic.eecs.berkeley.edu

Home Page: http://www-cad.eecs.berkeley.edu/~newton