Input/Output Behavior of Latches and Flip-Flops

Type

When Inputs

Sampled

When Outputs

Valid

Unclocked Latch

always

Tsu, Th

Relative to:

Tprop from

input change

-

Level-Sensitive

Latch

Tprop from

input change

Falling clock

edge

clock high

Positive edge

triggered flip-flop

Tprop from

rising clock edge

Rising clock

edge

clock low ® high

transition

Negative edge

triggered flip-flop

Tprop from

falling clock edge

Falling clock

edge

clock high ® low

transition

Master-slave

flip-flop

Tprop from

falling clock edge

Falling clock

edge

clock high ® low

transition

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