Albert Magyar

PhD Candidate in Computer Science at UC Berkeley

About Me

INTRODUCTION

I am a PhD Candidate in the ADEPT Lab at UC Berkeley, advised by Krste Asanović and Jonathan Bachrach. I work primarily on tools to improve productivity for hardware designers, including FIRRTL, a compiler framework for RTL design, and Chisel, a hardware description language embedded in Scala. My dissertation work involves developing CAD tools to automatically reduce resource utilization in FPGA simulation of ASIC RTL designs. This work is done as part of FireSim, an open-source FPGA simulation infrastructure that supports flexible co-simulation with software models.

Education

EDUCATION

Ph.D., Computer Science

University of California, Berkeley
August 2014 - Present

B.A., Computer Science

University of California, Berkeley
August 2008 - May 2013

B.S., Nuclear Engineering

University of California, Berkeley
August 2008 - May 2013

Work Experience

SKILLS AND RESPONSIBILITIES

Hardware Engineering Intern

Google
May 2017 - Dec 2017

Completed an R&D project related to RISC-V microcontroller SoC development. Worked across various domains, from RTL design, to chip-level integration and firmware porting. My experience led to the tapeout of a test chip.

  • Verilog and SystemVerilog for design
  • RISC-V firmware integration

Engineering Intern in VLSI

Ambarella
May 2012 - August 2012

Created a library for capturing high-level specifications of configuration registers and generating various downstream artifacts related to the resulting memory map. This project involved developing tools for automatic generation of bus and configuration access RTL, test vectors, and HTML documentation. I also was responsible for the RTL design of a few small, reusable blocks for macro-block video compression.

  • Verilog
  • Perl (with the Moose object system)

Documents

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