I am a PhD Candidate in the ADEPT Lab at UC Berkeley, advised by Krste Asanović and Jonathan Bachrach. I work primarily on tools to improve productivity for hardware designers, including FIRRTL, a compiler framework for RTL design, and Chisel, a hardware description language embedded in Scala. My dissertation work involves developing CAD tools to automatically reduce resource utilization in FPGA simulation of ASIC RTL designs. This work is done as part of FireSim, an open-source FPGA simulation infrastructure that supports flexible co-simulation with software models.
Completed an R&D project related to RISC-V microcontroller SoC development. Worked across various domains, from RTL design, to chip-level integration and firmware porting. My experience led to the tapeout of a test chip.
Created a library for capturing high-level specifications of configuration registers and generating various downstream artifacts related to the resulting memory map. This project involved developing tools for automatic generation of bus and configuration access RTL, test vectors, and HTML documentation. I also was responsible for the RTL design of a few small, reusable blocks for macro-block video compression.