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UCB Office 288
Cory Hall
Coverity
Suite 6500
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Education
Andreas received the Dipl-Ing. degree and the Dr.-Ing. habil degree in Electrical Engineering from the University of Technology at Ilmenau, Germany, in 1986 and 1990, respectively.
Professional Background
After graduation, from 1990 to 1991, Andreas worked at the Fraunhofer Institute of Microelectronic Circuits and Systems, Duisburg, on a project to automatically synthesize embedded microcontrollers. In 1991 he joined the IBM T.J. Watson Research Center where he worked until June 2000 on various projects in high-level and logic synthesis and hardware verification. Among others, he was the principal author and project leader of Verity, IBM's standard equivalence checking tool. From January 1998 until May 1999 Andreas visited the Department of Electrical Engineering and Computer Science at U.C. Berkeley. In July 2000 he joined the Cadence Berkeley Laboratories where he continues to work on synthesis and verification problems. Since July 2002, he is also adjunct professor at the University of California at Berkeley. In 2003 Andreas was awarded IEEE Fellow. In August 2003 Andreas became the Director of Cadence Laboratories and was also promoted to Cadence Fellow in 2004.
Publications
An Analysis of SAT-Based Model Checking Techniques in an Industrial Environment, 14th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods (CHARME 2005), Saarbrücken, Germany, October 2005, with N. Amla, X. Du, R. P. Kurshan, and K. McMillan.
Temporal Decomposition for Logic Optimization, 23rd IEEE International Conference on Computer Design (ICCD 2005), San Jose, California, USA, October 2005, with N. Kitchen.
Building a Better Boolean Matcher and Symmetry Detector, 14th IEEE/ACM International Workshop on Logic and Synthesis (IWLS 2005), Lake Arrowhead, California, USA, June 2005, with D. Chai.
Do We Waste Logic on Circuit Initialization?, 14th International Workshop on Logic and Synthesis (IWLS 2005), Lake Arrowhead, California, USA, June 2005, with N. Kitchen.
Early Research Experience with OpenAccess Gear: An Open Source Development Environment for Physical Design, 2005 ACM International Symposium on Physical Design (ISPD 2005), San Francisco, California, USA, April 2005, pp. 94-101, with C. Albrecht, P. Chong, I. L. Markov, D. A. Papa, R. A. Rutenbar, and Z. Xiu.
A Fast Pseudo-Boolean Constraint Solver, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 3, March 2005, with D. Chai.
Dynamic Transition Relation Simplification for Bounded Property Checking, IEEE/ACM International Conference on Computer Aided Design (ICCAD'04), San Jose, CA, November 2004
Physical Placement Driven by Sequential Timing Analysis, IEEE/ACM International Conference on Computer Aided Design (ICCAD'04), San Jose, CA, November 2004, with Philip Chong, and Aaron Hurst
Scalable Automated Verification via Expert-System Guided Transformations, Formal Methods in Computer-Aided Design (FMCAD'04), Austin, Texas, November 2004, with Jason Baumgartner, and Robert Kanzelman, Hari Mony, and Viresh Paruthi
Circuit-based Preprocessing of ILP and Its Applications in Leakage Minimization and Power Estimation, IEEE International Conference on Computer Design (ICCD'04), San Jose, CA, October 2004, with Donald Chai
Dynamic Transition Relation Simplification for Bounded Property Checking, International Workshop on Logic and Synthesis (IWLS'04), Temecula, CA June 2004
Performance and Area Optimization using Sequential Flexibility, International Workshop on Logic and Synthesis (IWLS'04), Temecula, CA June 2004, with Christoph Albrecht, and Pascal Witte
Enhanced Diameter Bounding via Structural Transformation, IEEE/ACM Design Automation in Europe (DATE'04), Paris, France, February 2004, with J. Baumgartner
Multi-Domain Clock Skew Scheduling, IEEE/ACM International Conference on Computer Aided Design (ICCAD'03), San Jose, CA, November 2003, pp. 801-808 with K. Ravindran, and E. Sentovich
CAMA: A Multi-Valued Satisfiability Solver, IEEE/ACM International Conference on Computer Aided Design (ICCAD'03), San Jose, CA, November 2003, pp. 326-333 with C. Liu, and M. W. Moskewicz
Structural Detection of Symmetries in Boolean Functions, IEEE International Conference on Computer Design (ICCD'03), San Jose, CA, October 2003, pp. 498-503, with A. Sangiovanni-Vincentelli, and G. Wang
A Fast Pseudo-Boolean Constraint Solver, ACM/IEEE Design Automation Conference (DAC'03), Anaheim, CA, June 2003, pp. 830-835 with D. Chai
Learning Schemes in 0-1 ILP, IEEE/ACM International Workshop on Logic Synthesis (IWLS'03), Laguna Beach, CA, June 2003, with D. Chai
The Best of ICCAD - 20 Years of Excellent in Computer-Aided Design, Kluwer Academic Publishers, 2003, ISBN 1-4020-7391-7, (Editor)
Robust Boolean Reasoning for Equivalence Checking and Functional Property Verification, IEEE Transactions on Computer-Aided Design, Vol. 21. No. 12, Dec. 2002, pp. 1377-1394, with M. Ganai, F. Krohm, and V. Paruthi
Minimum-Power Retiming for Dual-Supply CMOS Circuits, ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, (TAU'02), Monterey, CA, December, 2002, with K. Keutzer, and F. Sheikh
Property Checking via Structural Analysis, Conference on Computer Aided Verification (CAV'02), Paris, France, July 2002, with J. Baumgartner
Circuit-based Evaluation of the Arithmetic Transform of Boolean Functions; International Workshop on Logic Synthesis (IWLS'02), New Orleans, LA, June 2002, with E. Dubrova, and R. Krenz
Fine-Grain Conjunction Scheduling for Symbolic Reachability Analysis, Eighth International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS 2002), Grenoble, France, April 2002, pp. 312-326, with HoonSang Jin, and Fabio Somenzi.
Combinational and Sequential Equivalence Checking, Book chapter in "Logic Synthesis and Verification", Kluwer Academic Publishers, 2001, with C. van Eijk
Min-Area Retiming on Flexible Circuit Structures, IEEE/ACM International Conference on Computer Aided Design 2001 (ICCAD'01), San Jose, CA, November 2001, pp. 176-182, with J. Baumgartner
Sequential SPFDs, IEEE/ACM International Conference on Computer Aided Design 2001 (ICCAD'01), San Jose, CA, November 2001, pp. 84-90, with R. K. Brayton, and S. Sinha
Transformation-Based Verification Using Generalized Retiming, Conference on Computer Aided Verification (CAV'01), Paris, France, July 2001, pp. 104-117, with J. Baumgartner
Circuit-based Boolean Reasoning, Proceedings of the Design Automation Conference (DAC'01), Las Vegas, NV, June 2001, pp. 232-237, with M. Ganai, and V. Paruthi
Sequential SPFDs, International Workshop on Logic Synthesis (IWLS'01), Lake Tahoe, CA, June 2001, with R. K. Brayton, and S. Sinha
Retiming on Flexible Circuit Structures, International Workshop on Logic Synthesis (IWLS'01), Lake Tahoe, CA, June 2001, with J. Baumgartner
Design of Provably Correct Storage Arrays, Proceedings of the 14th International Conference on VLSI Design (VLSI Design'01), Bangalore, India, January 2001, pp 196-201
Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation, Proceedings of the IEEE International Conference on Computer Design (ICCD'00), Austin, TX, October 2000, pp. 459-464, with V. Paruthi
On-the-Fly Compression of Logical Circuits, International Workshop on Logic Synthesis (IWLS'00), Dana Point, CA, June 2000, with M. Ganai
Probabilistic State Space Search, IEEE/ACM International Conference on Computer Aided Design 1999 (ICCAD'99), San Jose, CA, November 1999, pp. 574-579, with R. K. Brayton, and K. McMillan
Model Checking Semi-Continuous Time Models Using BDDs, Federated Logic Conference (FloC'99) Workshop on Symbolic Model Checking (SMC'99), July, 1999, Trento, Italy, with S. Campos, E. M. Clarke, M. Minea, and M. Teixeira
SPFD-based Wire Removal in a Network of PLAs, International Workshop on Logic Synthesis (IWLS'99), Tahoe City, CA, June 1999, with R. K. Brayton, S. P. Khatri, A. Sangiovanni-Vincentelli, and S. Sinha
Enhancing Simulation with BDDs and ATPG, Proceedings of the Design Automation Conference (DAC'99), New Orleans, LA, June 1999, pp. 385-390, with A. Aziz, and M. Ganai
Equivalence Checking Using Cuts and Heaps, Proceedings of the Design Automation Conference (DAC'97), Anaheim, CA, June 1997, pp. 263-268, with F. Krohm
Validity Checking in the Theory of Equality with Uninterpreted Functions Using Finite Instantiations, International Workshop on Logic Synthesis (IWLS'97), Tahoe City, CA, May 1997, with R. K. Brayton, S. German, and R. Hojati
The Use of Random Simulation in Formal Verification, Proceedings of the IEEE International Conference on Computer Design (ICCD'96), Austin, TX, October 1996, pp. 371-376, with F. Krohm
Formal Verification of a PowerPC Microprocessor, Proceedings of the IEEE International Conference on Computer Design (ICCD'95), Austin, TX, October 1995, pp. 79-84, with P. D. Appenzeller
High-Level Synthesis in an Industrial Environment, IBM Journal of Research and Development, Vol. 39, No. 1/2, January/March 1995, pp. 131-148, with R. A. Bergamaschi, M. Z. Moricz, R. A. O'Connor, S. Prakash, D. S. Rao, and L. Stok.
Verity - A Formal Verification Program for Custom CMOS Circuits, IBM Journal of Research and Development, Vol. 39, No. 1/2, January/March 1995, pp. 149-165, with D. P. LaPotin, and A. Srinivasan
Grammar-Based Optimization of Synthesis Scenarios, Proceedings of the IEEE International Conference on Computer Design (ICCD'94), Boston, MA, October 1994, pp. 20-25, with L. P. P. P. van Ginneken
Error Diagnosis for Transistor-Level Verification, Proceedings of the Design Automation Conference (DAC'94), San Diego, CA, June 1994, pp. 218-224, with D. I. Cheng, D. LaPotin, and A. Srinivasan
A System for Production Use of High-Level Synthesis, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, September 1993, pp. 233-243, with R. Bergamaschi
Tuning of Logic Synthesis Scenarios, International Workshop on Logic Synthesis (IWLS'93) Tahoe City, CA, May 1993, pp. P7c1-P7c6, with L. P. P. P. van Ginneken
Timing Analysis in High-Level Synthesis, Proceedings of the IEEE/ACM International Conference on Computer Aided Design 1992 (ICCAD'92), Santa Clara, CA, November 1992, pp. 349-354, with R. A. Bergamaschi
A Methodology for Production Use of High-Level Synthesis, International Workshop on High-Level Synthesis (ISSS'92), Laguna Niguel, CA, November 1992, pp. 27-38, with R. A. Bergamaschi, D. Neumann, D. Reischauer, V. Venkataraman, and S. Wu
High-Level State Machine Specification and Synthesis, Proceedings of the IEEE International Conference on Computer Design (ICCD'92), Boston, MA, October 1992, pp. 536-539, with R. A. Bergamaschi
Control Optimization in High-Level Synthesis using Behavioral Don't Cares, Proceedings of the Design Automation Conference (DAC'92), Anaheim, CA, July 1992, pp. 657-661, with R. A. Bergamaschi, and D. Lobo
Last updated: Nov 28, 2005