Computer Science 152 - Basic Workview Office Tutorial

Prof. Robert Brodersen, Fall 1998

This tutorial will give you a quick walkthrough of the Workview Office environment on Windows NT 4.0. Since most of you used this environment in CS150 at U.C. Berkeley, this might be a review. We will be using a newer version of the software, however, so we recommend that you run this tutorial even if you used Workview Office plenty in CS150.

Note: VHDL, the hardware description language you will be using for most of this course, is not included in this tutorial. A new tutorial that covers VHDL syntax and the tools we will use will be provided later.

1. Create a new folder for this tutorial in your home directory. Home directories for this class are stored on the server Fischer. The cs152 folder on Fischer is mapped to the U: drive when you log in, and there is a shortcut on the desktop for accessing it. Open the U: drive, open your folder, and create a new folder in your home directory called tut1.
   
2. Create a new project. Open the project manager either from the Start Menu or from the Workview Office toolbar. Create a new project (either by clicking the New button or from the File menu) called tut1 in the folder you created above. When prompted to select FPGA libraries, click the Clear button before continuing (we will not be using FPGAs, sorry). When prompted to select ViewDraw libraries, click Add…. Type U:\cs152\lib (or Browse to the folder) in the Path box, and choose Readonly for its Type.
   
3. Create a new schematic in ViewDraw. Open ViewDraw either from the Workview Office toolbar or the Start Menu. If you are given a warning message about writing to the registry, ignore it and click OK. In ViewDraw, create a new schematic from the File menu or the toolbar called mymux.
   
4. Place gates to form your multiplexor. You will be building a 2:1 multiplexor out of two NAND gates, a NOR gate, and four INV1X (normal drive inverters). If you feel like optimizing your design to reduce gates, feel free, but this is the direct, no-thinking approach. The logic equation for a mux is OUT=A*SEL#+B*SEL, where the ‘#’ means ‘NOT SEL’. Recall that a mux, which you will see a lot of this semester, passes one of the two input signals based on its select input. To place a gate, either add a component from the Add menu or click the button with a gate symbol on the left toolbar. To place a gate, select the U:\cs152\lib library and drag the appropriate gate onto your schematic.
   
5. Connect the gates with nets. Draw nets between pins on your gates using the net tool. Access this tool in the Add menu or from the left toolbar (nets are the thinner red lines, the longer ones are busses which you will use later). You should get used to naming all you nets. To add a name label to a net, double click the net and add a descriptive name. When you are done make sure you first Save and Check your schematic, then Save it (they do different things).
   
6. Create a symbol to represent your schematic. You will need to create many symbols this semester, so this is a good one to get started on early. Create a new symbol (if you are adventurous, you can use the Symbol Wizard, but I find it harder to use) WITH THE SAME NAME AS THE SCHEMATIC, in this case, mymux. By doing this, you logically connect the net names in the schematic to pin names on the symbol.
   
7. Add pins to the symbol. Add pins to your symbol using the pin tool from the Add menu or the pin button on the left toolbar. Give the pins the same name as the two inputs, the select signal, and the output of the mux. Access each pin’s attributes by double clicking on it. Go to the Attributes tab and add PINTYPE=IN or PINTYPE=OUT depending on the type of signal (you will have three in and one out). Save your symbol and close all windows in ViewDraw.
   
8. Create a new schematic to test your mux. Create a new schematic called mymuxtest. Place your new mux symbol on the schematic and add nets to its pins. Label the nets A, B, SEL, and OUT. Save and Check, Save the schematic, and you can close ViewDraw.
   
9. "Compile" your schematic with ViewVSM. Open ViewVSM either from the Start Menu or the Workview Office toolbar. Browse… for the design, and choose the mymuxtest.1 file. Click Create Netlist and close the window when it is done. You design is now ready to simulate.
   
10. Simulate your design with Digital Fusion and Vwaves. Fusion and Vwaves are the new versions of ViewSim and ViewTrace respectively. Get to know them; they will be your friends. Open Digital Fusion from the Start Menu or the Workview toolbar. When Fusion opens, load your design from the File menu or the toolbar. Click the Schematic box and Browse… for your mymuxtest.vsm file. Open this file and continue. The Hierarchy Viewer will pop up, which lets you browse your entire design by net and component. We will tie the A and B inputs low and high and use the SEL signal as a clock to watch the output switch between A and B. Use the following commands in Fusion if you forget:
    
    clock sel 0 1
    stepsize 5ns
    l a
    h b
    watch a b sel out
    wave mymuxtest.wfm a b sel out
    cycle 10
    
    Vwaves will open your design and plot the waveforms as the "clock" cycles for 10 periods. You can use Vwaves to measure the timing and delay of your mux. You’ll notice that a green bar snaps to every transition in a signal. If you left-drag the mouse between transitions, Vwaves will measure the difference for you. You can also use the markers to point out critical times in your simulation. Experiment with the various features of Vwaves and get used to the interface. You should easily be able to see the internal delay of your mux by measuring the amount of time it takes for the output to change after the select signal changes.
    
11. Now you’re ready for Lab 3, close all windows and create a new project for Lab 3 with Project Manager.