Computer Science 152 - VHDL Tutorial

Prof. Robert Brodersen, Fall 1998

This tutorial is designed to get you familiar with the VHDL tools available in Workview Office. No real attempt is made here to explain VHDL. At this point, we assume that you have run through the basic tutorial, finished Lab 3, and have a firm grasp on the Workview environment. If you have trouble following some of these instructions, rerun the last tutorial or come to office/lab hours.

We will be using a subset of VHDL that is supported in Workview. VHDL is used to model everything from microprocessors to chipsets to signal processors. This makes it extremely complex as a whole. We will only be using a small portion of the total language in this class. After learning VHDL, I am told that Verilog (the other HDL standard) comes easily. By the way, it would be a good idea to include "VHDL" on your resumes starting now.

Enough talk... Log into a CS152 class account and let's get started.

  1. Open up a new folder and project called "vhdl_tut" in your home directory. You will also want to include the U:\cs152\lib folder in your search path as you did in the last assignment (this would be a good idea for all future assignments).
  2. Create a new folder called "behv" in your project folder. This is where you will store all your VHDL code. The directory actually stands for "behavioral", since the VHDL code you write describes the behavior of each module in simulation.
  3. Copy the VHDL to your project and examine the code. Copy the alu.vhd and halfadder.vhd files from U:\cs152\lib\behv to your behv directory. These files are VHDL source code for a full MIPS ALU and halfadder circuit, respectively. Open these files in HDLpad. It would be most convenient of you double-clicked the file and chose HDLpad to be the default viewer (leave the box checked). You will only have to do this once each time you log in. The halfadder code is very verbose. It tells you about most of the different parts of a VHDL module. You will not need to use all of those statements, but there are some fairly useful comments in there. The ALU is a generic, simplified MIPS ALU. It is in a format similar to what we expect you to use. For more help on writing VHDL code, please come to office hours since it is not easy to teach within a tutorial, and you will be using it A LOT.
  4. Compile the VHDL source code. You will need to compile VHDL from a DOS command prompt. Open a DOS command window from the Start Menu and change to your project directory. You should be in the top directory, "vhdl_tut", one above the "behv" directory. Type the command vhdl halfadder (it automatically knows to check in the "behv" folder). You will see a summary of the compiler's warnings. For now, you can ignore all EXTENSION warnings. These are details of the Workview subset that do not matter unless we upgrade the VHDL methods later in the semester. Proceed to compile the ALU module by typing vhdl alu. The compiler creates *.lis files in the project folder and *.vli files in the "behv" folder.
  5. Create symbols for each VHDL module. Workview has a program that automatically creates symbols based on your VHDL code. Before making the symbols, open ViewDraw to create the proper structure in your project folder. At the NT command prompt, type vhdl2sym -subset halfadder  followed by vhdl2sym -subset alu  to create symbols for your code. Again, it knows to look in the "behv" folder and put symbols in the "sym" folder. Do not forget the "-subset" argument or else bad things will happen. Verify that the new symbols are created. Open a symbol in ViewDraw to check it out. The symbols will always be blocks with arbitrarily ordered pins. You will want to refine the symbol to make your design more readable. Also, you'll notice that the PINORDER attribute is visible. Select and right-click outside the symbol border and select Properties. Go to the Attributes tab and change the PINORDER attribute to Invisible. You will want to do this for each symbol.
  6. Create a new schematic with your VHDL-based symbols. Create a new schematic and place the new symbols, naming all nets. Save/Check and Save the schematic.
  7. Create a netlist using ViewVSM. Nothing should be new here.
  8. Open your schematic for simulation in Digital Fusion. When you load your design, choose only your schematic for simulation. Note that there is a VHDL option. This is for testing VHDL modules by themselves, but requires the newer method of using VHDL in Workview. This feature alone is one reason why we may upgrade the VHDL methods later.
  9. Experiment with simulating and tracing waveforms, especially with respect to delay. Use Fusion and Vwaves to experiment with the design. Notice how long it takes data to pass through each module. Compare this to the values specified in the VHDL source code for each component. This analysis will give you nightmares for (10) weeks to come, so learn to love it. VHDL works by running a process whenever any of the "sensitive" inputs to that process change. Consequently, you tell the component how long it will take for the data to become valid on whatever outputs are supposed to change. This fixed internal delay is the model we will use all semester, but please don't forget that fan-out and fan-in are bad.
  10. You're certified VHDL experts. Go ahead on Lab 4.