SPACE: SYMBOLIC PROCESSING IN ASSOCIATIVE COMPUTING ELEMENTS

Abstract:

The SPACE chip implements 14836-bit Content Addressable Parallel Processors (CAPPs). In the PADMAVATI prototype system, a hierarchy of packaging technologies cascade multiple SPACE chips to form a 170496 processor array.

Primary applications for SPACE are AI algorithms that require fast searching and processing within large, rapidly changing data structures. The PADMAVATI prototype has a peak performance of 32b comparisons per second. Primitive parallel search and write instructions can be composed into arbitrarily complex arithmetic and logical operations, allowing SPACE to be used as a powerful SIMD processor.

In this paper we describe in detail the architecture and implementation of SPACE.

Denis B. Howe and Krste Asanovic

• INTRODUCTION
• INSTRUCTION SET ARCHITECTURE
• SPACE IMPLEMENTATION
• PERFORMANCE
• SUMMARY
• ACKNOWLEDGEMENTS
• References
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