Choice coordination is one of a class of problems that arise in distributed computing. The problem sounds very easy: There are n processors and m choices, and all the processors have to agree on one of the choices. E.g. there may be m parallel programs that can be run, all of which require all n processors. The processors have to decide which one to run first. There are many other similar cases. You want the processors to work together, but in order to do that, they need to all agree on what to do.
But the solution is not so obvious. Its tempting to take a vote, or let one processor pick, but in classical ways of doing this, you end up relying on one processor to choose or tally the votes, and there is a risk of corruption, or of failure if there is a bug in that processor. A good distributed protocol should be truly distributed, that is, it shouldn’t rely on special action by any particular processor.
The model of computation is shown below. There is a set of m registers that all the processors can read or write to.
You don’t need to take the model too literally. The shared registers don’t have to all be in one placed. They may be distributed among the processors. The above picture shows the logical, not the physical structure.
Every processor can write to any register. Since this may cause contention, there is a locking mechanism attached to each register so that if multiple processors try to access it, only one of them is allowed to. The others wait until the first processor’s lock is released, and then contend for access again.
At the end of the protocol, there should be a unique register with the special symbol Ö in it. We measure the complexity of a choice coordination protocol as the number of read-write operations that it requires.
Lemma Any deterministic algorithm that solves the choice coordination problem requires W (n1/3) operations.
But randomized protocols don’t have that limitation. In fact they are much faster on average. We will describe a protocol such that for any constant c, the probability that agreement is reached in c steps is at least 1 – 2-W (c). That is, if X is the running time to agreement, then X is a geometric random variable (or more correctly, there is a geometric random variable whose probability distribution bounds X from above).
There are two registers C0 and C1, and two processors P0 and P1. The registers are assumed to be initialized to zero. Each processor has a local variable Bi, which is also zero initially.
Here’s some pseudo-code for the algorithm:
Input: Registers C0 and C1 initially zero
Output: Exactly one of the registers has the value Ö
To understand the algorithm, first notice that the two processors are alternating access to the registers. Processor 1 accesses register 1 first, then it accesses register 0 on the next iteration, and then register 1 again. Processor 0 always accesses the other register.
Now notice that if a processor doesn’t halt, it goes through step 2(c). That means it picks a random bit for Bi and saves it in register Ci. Each time we start an iteration, since the processors have swapped registers, Ri contains the bit that the other processor wrote, which is still the contents of B1-i. Step 2(b) is therefore the case where the current register (in Ri) contains a 0, and the other register (whose value is saved in Bi) contains a 1. The registers therefore contain different values and its safe to write a Ö into the current register. The other processor will have Ri = 1 and Bi = 0, so it will not write a Ö .
When neither processor halts, both of them write a random bit into the registers. If two different bits are written, then one of the processors will halt on the next step, and the other on the step after that. The probability of different bits on a given step is just ½. The running time is therefore a geometric random variable with probability p, and the expected running time is 4 (2 to get different bits, and two more for both processors to halt). steps. The probability that it takes more than c+2 steps to halt is 1 – 2-c.
The main difference between this case is the addition of time stamps to allow for the fact that the two processors are not synchronized. The time stamp in this case isn’t really a measure of exact time, but of "iteration number". But even that can be different for the two processors.
Each processor keeps two time variables. Ti is like processor i’s clock. ti is the time that processor i reads from its current register, which will be the other processor’s time. The algorithm follows:
Input: Registers C0 and C1 initialized to <0,0>
Output: Exactly one of the two registers has the value Ö
b) Ti < ti: Set Ti ¬ ti and Bi ¬ Ri
c) Ti > ti: Write Ö into the current register and halt.
The analysis for the asynchronous version is very similar to the synchronous version. When Ti = ti in particular, steps 2(d) and 2(e) of the asynchronous algorithm correspond to steps 2(b) and 2(c) of the synchronous algorithm.
The new cases are 2(b) and 2(c) of the asynchronous algorithm. For step 2(b) the other processor must be at least one step ahead (ti > Ti). Moving Ri into Bi ensures that at the end of this round, Bi will be equal to the contents of the register that we just left. We don’t write anything new into this register because it has already been read by the other processor in the ti round.
Step 2(c) takes a short-cut to completing the protocol. Since the processor Pi is at least one time step ahead, if it writes the character Ö into the current register, the other processor will read it on the next time step and halt.