Yield-constrained Digital Circuit Sizing via Sequential Geometric Programming

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Authors: Yu Ben, Laurent El Ghaoui, Kameshwar Poolla, Costas J. Spanos.

Status: Appeared in the Proceedings of the International Symposium on Quality Electronic Design (ISQED), 2010.

Abstract: Circuit design under process variation can be formulated mathematically as a robust optimization problem with a yield constraint. Existing methods force designers to either resort to overly simplified circuit performance model, or rely on simplistic variability assumptions. On the other hand, accurate yield estimation must incorporate a sophisticated variability model that recognizes both systematic and random components at various levels of hierarchy. Unfortunately, such models are not compatible with existing optimization solutions. To solve the problem, we propose the sequential geometric programming method, which consists of iterative usage of geometric programming and importance sampling. It is capable of handling an arbitrary variability model. The proposed method is shown to be able to achieve the desired yield without overdesign, and solve circuits with thousands of gates within reasonable amount of time.

Bibtex reference:

@inproceedings{BEPS:10,
  author    = {Yu Ben and
               Laurent {El Ghaoui} and
               Kameshwar Poolla and
               Costas J. Spanos},
  title     = {Yield-constrained digital circuit sizing via sequential
               geometric programming},
  booktitle = {ISQED},
  year      = {2010},
  pages     = {114-121},
}