Chetan Kumar Dabhi, PhD, Senior Member IEEE

Staff Engineer - pSemi, A Murata Company | Former Postdoctoral Fellow at University of California Berkeley (BSIM Group)

Chetan Kumar Dabhi

Contact: dabhi@berkeley.edu, chetan.dabhi2013@gmail.com, cdabhi@psemi.com

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I received my PhD from IIT Kanpur and M.Tech degree from NIT Surat. I have served as an "Adjunct Assistant Professor" at NIT Nagpur, and received B. Tech from Shantilal Shah Eng. Collage, Bhavnagar University (Gujarat Technological University).
Throughout my career, I've concentrated on practical solutions involving device measurements in collaboration with the semiconductor industry. I'm known for quickly mastering new skills, comprehending complex mathematical concepts, and developing efficient test-driven EDA solutions. A natural leader and mentor.
News:

Developed a Symmetric BSIM-SOI 100.1.0 model that is accurate, fast, and robust. Created new compact models for advanced node BSIM-CMG.

During my postdoctoral tenure with the BSIM Group at UC Berkeley, I specialize in developing and supporting industry-standard compact models for diverse semiconductor devices, including SOI FETs, FinFETs, and Bulk FETs (BSIM-SOI, BSIM-IMG, BSIM-BULK, and BSIM4). These models, integral to major commercial SPICE simulators, facilitate precise and efficient circuit design and simulation.

A notable accomplishment is the creation of the Dynamic Depletion SOI FETs BSIM compact model tailored for RF designs/PDK. This model is now incorporated into widely used commercial circuit simulators such as HSPICE, ADS, Spectre, AFS, and more.

Armed with a Ph.D. in Microelectronics from IIT Kanpur, my doctoral research delved into physics-based leakage modeling and negative capacitance modeling for advanced technology nodes like FinFET, UTBB-FDSOI, and GAA. I've contributed to more than 35 publications in IEEE journals and conferences, focusing on enhancing FinFET/GAA, SOI, BULK FET modeling. My research interests encompass alternative device structures, physics, and materials for deeply scaled CMOS, along with compact modeling of semiconductor devices.

Publication List Awards and Honors Research Updates & Collaboration Professional Activities & Skills Books & Talk Delivered

Publication List

Journal Articles:
  1. Chetan Kumar Dabhi, Girish Pahwa, Sayeef Salahuddin, Chenming Hu, "Boltzmann-Statistics Aware Non-Quasi-Static-Charge Model for IC Simulations", under revision in, IEEE Transactions on Electron Devices, 2024.
  2. D. Nandi, C. K. Dabhi, D. Rajasekharan, N. Karumuri, S. Turuvekere, A. Dutta, B. Swaminathan, S. Srihari, C. Hu, Y. S. Chauhan, "Utilizing Symmetric BSIM-SOI SPICE model for Dynamically Depleted RF SOI T/R Switches and Logic Circuits", in, Journal of Electron Device Society, 2024.
  3. D. Nandi, C. K. Dabhi, D. Rajasekharan, N. Karumuri, S. Turuvekere, S. Choppalli, A. S. Pratiyush, C. Hu, and Y. S. Chauhan, "Physical Insights and Accurate Modeling of Transconductance in Body-contacted Dynamically Depleted SOI MOSFETs ", in IEEE Transactions on Electron Devices, 2024.
  4. C. T. Tung, C. K. Dabhi, S. Salahuddin, C. Hu, "A Versatile Compact Model of Resistive Random-Access Memory (RRAM)  ", accepted in Solid State Electronics, 2024.
  5. C. T. Tung, A. Pampori, C. K. Dabhi, S. Salahuddin, C. Hu, "A Novel Neural Network-based Transistor Compact Model Including Self-Heating", accepted in IEEE Electron Device Letters, 2024.
  6. S. Chatterjee, S. Kumar, A. Gaidhane, C. K. Dabhi, Y. S. Chauhan, and H. Amrouch, "Temperature and Variability-Aware Compact Modeling of Ferroelectric FDSOI FET for Memory and Emerging Applications", accepted in Solid State Electronics, 2024.
  7. A. Sharma, Y. Hayat, G. Pahwa, C. K. Dabhi, R. Goel, A. Agarwal, V. Kubrak, M. Tang, M. Treiber, C. Hu, Y.S. Chauhan, "Compact Modeling of Impact Ionization and Conductivity Modulation in LDMOS Transistors", accepted in,IEEE Transactions on Electron Devices, 2024.
  8. Chetan Kumar Dabhi, D. Rajasekharan, G. Pahwa, D. Nandi, N. Karumuri, S. Turuvekere, A. Dutta, B. Swaminathan, S. Srihari, Y. S. Chauhan, S. Salahuddin, C. Hu, "Symmetric BSIM-SOI – Part I: A Compact Model for Dynamically Depleted SOI MOSFETs", in,IEEE Transactions on Electron Devices, 2024.
  9. Chetan Kumar Dabhi, D. Nandi, K. Nandan, D. Rajasekharan, G. Pahwa, N. Karumuri, S. Turuvekere, A. Dutta, B. Swaminathan, S. Srihari, Y. S. Chauhan, S. Salahuddin, C. Hu, "Symmetric BSIM-SOI – Part II: A Compact Model for Partially Depleted SOI MOSFETs" in, IEEE Transactions on Electron Devices, 2024.
  10. Chetan Kumar Dabhi, Girish Pahwa, Sayeef Salahuddin, Chenming Hu, "Boltzmann-Statistics Aware Non-Quasi-Static-Charge Model for IC Simulations", under revision in, IEEE Transactions on Electron Devices, 2024.
  11. S. Kumar, S. Chatterjee, Chetan Kumar Dabhi, Y. S. Chauhan, and H. Amrouch, "Non-Traditional Design of Dynamic Logics using FDSOI for Ultra-Efficient Computing"", IEEE Journal of Exploratory Solid-State Computational Devices and Circuits, 2023.
  12. S. Chatterjee, S. Kumar, A. Gaidhane, Chetan Kumar Dabhi, Y. S. Chauhan, and H. Amrouch, "Ferroelectric FDSOI FET Modeling for Memory and Logic Appliations"", Solid State Electronics , 2023.
  13. Chetan Kumar Dabhi, A. S. Roy, L. Yang and Y. S. Chauhan, "Anomalous GIDL Effect with Back Bias in FinFET: Physical Insights and Compact Modeling"", accepted, IEEE Transactions on Electron Devices, 2021.
  14. O. Prakash, G. Pahwa, Chetan Kumar Dabhi, Y. S. Chauhan, and H. Amrouch, "Impact of Self-Heating on Negative-Capacitance FinFET: Device-Circuit Interaction"", IEEE Transactions on Electron Devices, 2021.
  15. Chetan Kumar Dabhi, S. S. Parihar, A. Dasgupta, and Y. S. Chauhan, "Compact Model of Negative-Capacitance FDSOI FETs for Circuit Simulations"", IEEE Transactions on Electron Devices, 2020.
  16. F. Bellando, Chetan Kumar Dabhi, A. Saeidi, C. Gastaldi, Y. S. Chauhan, and A. M. Ionescu, "Subthermionic Negative Capacitance Ion Sensitive Field-Effect Transistor"", Applied Physics Letters , 2020.
  17. H. Amrouch, G. Pahwa, A. D. Gaidhane, Chetan Kumar Dabhi, F. Klemme, O. Prakash and Y. S. Chauhan, "Impact of Variability on Processor Performance in Negative Capacitance FinFET Technology"", IEEE Transactions on Circuits and Systems-I , 2020.
  18. Chetan Kumar Dabhi, Ananda S. Roy, Yogesh S. Chauhan, "Compact Modeling of Temperature-Dependent Gate-Induced Drain Leakage Including Low-Field Effects"", in "IEEE Transactions on Electron Devices " Vol. 66, Issue 7, Pages 2892-2897, 2019.
  19. Chetan Kumar Dabhi, A. Dasgupta, P. Kushwaha, H. Agarwal, C. Hu and Y. S. Chauhan, "Modeling of Induced Gate Thermal Noise Including Back-Bias Effect in FDSOI MOSFET"" in IEEE Microwave and Wireless Components Letters , vol. 28, no. 7, pp. 597-599, July 2018.
  20. Subrat Mishra, Hussam Amrouch, Jerin Joe, Chetan Kumar Dabhi, Karansingh Thakor, Yogesh S Chauhan, Jörg Henkel, Souvik Mahapatra, "A Simulation Study of NBTI Impact on 14-nm Node FinFET Technology for Logic Applications: Device Degradation to Circuit-Level Interaction,"" in IEEE Transactions on Electron Devices, vol. 66, no. 1, pp. 271-278, Jan. 2019.
  21. S. Mishra, N. Parihar, A. R, Chetan Kumar Dabhi, Y. S. Chauhan and S. Mahapatra, "NBTI-Related Variability Impact on 14-nm Node FinFET SRAM Performance and Static Power: Correlation to Time Zero Fluctuations,"" in IEEE Transactions on Electron Devices, vol. 65, no. 11, pp. 4846-4853, Nov. 2018.
  22. A Thirunavukkarasu, Hussam Amrouch, Jerin Joe, Nilesh Goel, Narendra Parihar, Subrat Mishra, Chetan Kumar Dabhi, Yogesh S Chauhan, Jörg Henkel, Souvik Mahapatra , "Device to Circuit Framework for Activity-Dependent NBTI Aging in Digital Circuits,"" in IEEE Transactions on Electron Devices, vol. 66, no. 1, pp. 316-323, Jan. 2019.
  23. Chetan Kumar Dabhi, Ganesh C Patil , "Underlap channel silicon-on-insulator quantum dot floating-gate MOSFET for low-power memory applications"", "Journal of Computational Electronics ", Volume 15, Issue 4, Pages 1563-1569, 2016.
  24. Neha Barothiya, Chetan Kumar Dabhi, Ganesh C. Patil, "A Novel Channel Engineered Continuous Floating Gate MOSFET for Memory Applications"", "Journal of Nanoelectronics and Optoelectronics ", Volume 14, Number 5,, pp. 606-613, May 2019.
Conference Articles:
  1. D. Nandi, C. K. Dabhi, D. Rajasekaran, N. Karumuri, S. Turuvekere, B. Swaminathan, S. Srihari, A. Dutta, C. Hu, and Y. S. Chauhan, "Validation of Dynamically Depleted Symmetric BSIM-SOI Compact model for RFSOI T/R Switch Applications", IEEE Electron Devices Technology and Manufacturing Conference (EDTM), 2024.
  2. Y. H. Zarkob, A. Sharma, G. Pahwa, D. Nandi, C. K. Dabhi, V. Kubrak, B. Peddenpohl, M. Tang, C. Hu and Y. S. Chauhan, "Compact Modeling and Experimental Validation of Reverse Mode Impact Ionization in LDMOS Transistors within the BSIM-BULK Framework", IEEE Electron Devices Technology and Manufacturing Conference (EDTM), India, Mar. 2023.
  3. G. Pahwa, A. Dasgupta, C. T. Tung, M.Y. Kao, C. K. Dabhi, S. Sarker, S. Salahuddin and C. Hu, "Compact Modeling of Emerging IC Devices for Technology-Design Co-development" IEEE International Electron Devices Meeting (IEDM), San Francisco , 2022. (Invited)
  4. A. Sharma, Y. H. Zarkob, R. Goel, C. K. Dabhi, G. Pahwa, C. Hu, and Y. S. Chauhan, "Recent Enhancements in the Standard BSIM-BULK MOSFET Model" IEEE International Conference on Emerging Electronics (ICEE), Bengaluru , Dec. 2022.
  5. Chetan K. Dabhi, Girish Pahwa, Sayeef Salahuddin, and Chenming Hu, "Compact Model for Trap Assisted Tunneling based GIDL",Device Research Conference (DRC), Ohio , USA, June 26-29, 2022.
  6. Swetaki Chatterjee, Shubham Kumar, Amol Gaidhane, Chetan K. Dabhi, Yogesh S. Chauhan, Hussam Amrouch, "Ferroelectric FDSOI FET Modeling for Memory and Logic Applications", International Conference on Simulation of Semiconductor Processes and Devices (SISPAD) , Granada, Spain., Sept. 6-8 - 2022 ->Converted to Journal paper
  7. S. Kumar, S. Chatterjee, C. K. Dabhi, H. Amrouch, and Y. S. Chauhan, "A Novel Approach to Mitigate Power Side-Channel Attacks for Emerging Negative Capacitance Transistor Technology" 20th IEEE International NEWCAS Conference, Québec , Canada, June 2022.
  8. S. Chatterjee, S. Kumar, A. D. Gaidhane, C. K. Dabhi, H. Amrouch, and Y. S. Chauhan, "Modeling of Fe-FDSOI FET for Memory and Neuromorphic Applications", DATE (Design, Automation and Test in Europe Conference) Workshop on Ferroelectronics, Mar. 2022.
  9. S. Kumar, S. Chatterjee, C. K. Dabhi, H. Amrouch, and Y. S. Chauhan, "Novel FDSOI-Based Dynamic XNOR Logic for Ultra-Efficient High-Dense Computing" IEEE International Symposium on Circuits & Systems (ISCAS) , Austin, USA, June, 2022.
  10. O. Prakash, C. K. Dabhi, Y. Chauhan, and H. Amrouch, "Transistor Self-Heating: The Rising Challenge for Semiconductor Testing" IEEE VLSI Test Symposium (VTS’21) , April 2021.
  11. Chetan. K. Dabhi, P. Kushwaha, H. Agarwal, S. S. Chauhan, C. Hu, and Y. S. Chauhan, "Physical Analysis of Non-monotonic DIBL Dependence on Back Gate Bias in Thick Front Gate Oxide FDSOI MOSFETs" IEEE SOI–3D–Subthreshold Microelectronics Technology Unified Conference (S3S) , San Jose, USA, Oct. 2019.
  12. V. Kumar, Chetan. K. Dabhi, S. Singh Parihar and Y. S. Chauhan, "Analysis and Compact Modeling of Drain-Extended FinFET " 2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India) , Hyderabad, India, 2019, pp. 97-101. doi: 10.1109/MOS-AK.2019.8902458
  13. P. Kushwaha, H. Agarwal, Chetan. K. Dabhi, Y.-K. Lin, J. P. Duarte, C. Hu, and Y. S. Chauhan, "A Unified Flicker Noise Model for FDSOI MOSFETs Including Back-bias Effect" IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT) , Bengaluru, India, Mar. 2018.
  14. Chetan. K. Dabhi, P. Kushwaha, A. Dasgupta, H. Agarwal and Y. S. Chauhan, "Impact of back plane doping on RF performance of FD-SOI transistor" 3rd International Conference on Emerging Electronics (ICEE), Mumbai, 2016, pp. 1-4. doi: 10.1109/ICEmElec.2016.8074584
  15. Chetan. K. Dabhi, A. Dasgupta and Y. S. Chauhan, "Computationally efficient analytical surface potential model for UTBB FD-SOI transistors" 3rd International Conference on Emerging Electronics (ICEE), Mumbai, 2016, pp. 1-4. doi: 10.1109/ICEmElec.2016.8074575

Awards and Honors

  • Received the Outstanding "Teaching Assistant" award for my contribution to EE 210 MICROELECTRONICS - I in Semester-I, 2018
  • Ph.D. Fellowship MHRD (GOVT. OF INDIA) Jul. 2016 – Mar. 2021
  • Ministry of Human Resources (GOVT. OF INDIA) Scholarship for M.Tech degree.
  • IIT Kanpur travel grant for invited talk at MOS-AK modeling workshop, Chengdu, China.
  • First Rank in Bhavnagar University in UG First year.
  • Got 98.466 Percentile GATE (Graduate Aptitude Test in Engineering), 2012.
  • Included in IEEE TED Golden list of reviewers for 2019 -2023
  • Reviewer, IEEE Electron Device Letters (EDL)
  • Reviewer, IEEE Transactions on Electron Devices (TED)
  • Reviewer, Journal of Computational Electronics (JCEL)
  • Reviewer, IEEE Transactions on Circuits and Systems (TCAS)
  • Reviewer, Solid State Electronics Journal (SSE)
  • Reviewer, IEEE ICEE, IEEE EDTM

Research Updates & Collaboration

Research Updates:

    Here is the list of my research work that is going on under the supervision of Prof. Chenming Hu, UC Berkeley.
  • Developed the Symmetric BSIM-SOI/ Dynamic Depletion (DD) -SOI Compact model Development for RF PDK (CMC - Compact Model Coalition)
  • Unified RRAM Compact model development
  • BSIM Model Development.
  • Compact model development of GIDL for nano scale FinFET / GAA Devices.
  • Improved NQS Modeling.

Collaborations:

  • Prof. Yogesh S. Chauhan, IIT Kanpur
  • Prof. Souvik Mahapatra, IIT Bombay. - Compact model development for aging analysis at circuit/system level
  • A Compact Model Developement with Intel Corporation, Hillsboro, OR, USA.
  • Dr.-Ing. Hussam Amrouch , Universität Stuttgart, Germany
  • Prof. Adrian Ionescu, The Nanoelectronic Devices group (NANOLAB), EPFL, Lausanne (Switzerland)

Professional Activities & Skills

    Professional Activities:

    • Senior Member, IEEE
    • IEEE EDS Member

    Key Skills:

    • Core Device Model Development for state-of-the-art devices in Verilog-A
    • On-wafer and packaged device DC-IV, CV, Pulsed IV, S-Parameter measurements. DC/CV measurements using Keysight B1500/B1505. S-Parameter using a Keysight PNA-X (N5244A)
    • Parameter Extraction for the BSIM-CMG, BSIM-IMG and BSIM-HV model using Keysight IC-CAP and ADS.
    • TCAD simulations of state-of-the-art devices (Sentaurus TCAD, Silvaco TCAD)
    • Programming Languages: C, Matlab, Verilog-A, LATEX, Python, Machine Learning algorithms for parameter extraction.

    Skills:

    • Clean Room Experience: At INUP, IIT Bombay via Micro-fabrication Lab course: Exposure to Silicon MOSCAP fabrication processes: RCA Cleaning, Dry Oxidation, Lithography and etch, Plasma Immersion Ion Implantation, Metal Deposition, Back- side Etching and Metallization.
    • Software skills: TCAD Sentaurus / Silvaco, Mentor Graphics, NGSpice, ICCAP, Cadence , VHDL, Verilog, MATLAB.
    • Hardware Experience: Keithley SMU, Keil 8051, 8085 Microprocessor board, Cascade probe station, Parameter analyser B1505, Vector Network Analyser.

Books & Talks Delivered

Books Chapters:

Talk Delivered:

  • Delivered talk on ”Improved NQS Modeling at Industry Advisory Board Meeting, Berkeley Device Modeling Center (BDMC), UC Berkeley, 1st Dec. 2021.
  • Delivered talk on ”GIDL compact model at advanced technology nodes”, Berkeley Device Modeling Center (BDMC), UC Berkeley, 16th Sept. 2021.
  • Delivered talk on “BSIM-IMG: Industry Standard Model with Fast and Extended Range Core Including Improved Mobility and Noise models” in Compact Modeling Workshop (MOS-AK), Chengdu, China, 2019.
  • Speaker in IEEE S3S Conf. 2019, San-Jose, USA, on the research paper, “Physical Analysis of Non-monotonic DIBL Dependence on Back Gate Bias in Thick Front Gate Oxide FDSOI MOSFETs”.
  • Speaker in IEEE CONECCT 2018, Banglore, India, on the research paper, “A Unified Flicker Noise Model for FDSOI MOSFETs Including Back-bias Effect”.
  • Speaker in IEEE ICEE 2016, Mumbai, India, on the research paper, “Impact of Back Plane Doping on RF Performance of FD-SOI Transistor using Industry Standard BSIM-IMG Model”.
  • Poster on “Computationally efficient Analytical Surface Potential model for UTBB FD-SOI Transistors” ICEE 2016 in Indian Institute of Technology Bombay, Dec. 2016.