Title: Impact of Memory System Design on Communication Performance

Idea: In building active message layers on a range of platforms, we find
that the critical design decisions are driven by the performance of 
aspects of memory systems that receive very little attention in the
ISCA community: cache miss penalties, uncached accesses, cache-to-cache
tranfer costs, memory bus speed, and DMA.

Platforms:
	SS 10s with L2, SS 20s w/o L2, Ultrasparc (?)
	Meiko slow and meiko fast
	Paragon
	Maybe sun MPs

Data:
	Memory Hierarchy
	Uncached accesses
	Cache-to-cache latency
	DMA performance

Analysis:
	Show how these impact the design and the ultimate performance
	of the AM layers