Maintaining Inclusion
The two caches (L1, L2) may choose to replace different block
- Differences in reference history
- set-associative first-level cache with LRU replacement
- example: blocks m1, m2, m3 fall in same set of L1 cache...
- Split higher-level caches
- instruction, data blocks go in different caches at L1, but may collide in L2
- what if L2 is set-associative?
- Differences in block size
But a common case works automatically
- L1 direct-mapped, fewer sets than in L2, and block size same