Implementing LL-SC
Lock flag and lock address register at each processor
LL reads block, sets lock flag, puts block address in register
Incoming invalidations checked against address: if match, reset flag
- Also if block is replaced and at context switches
SC checks lock flag as indicator of intervening conflicting write
- If reset, fail; if not, succeed
Livelock considerations
- Don’t allow replacement of lock variable between LL and SC
- split or set-assoc. cache, and don’t allow memory accesses between LL, SC
- (also don’t allow reordering of accesses across LL or SC)
- Don’t allow failing SC to generate invalidations (not an ordinary write)
Performance: both LL and SC can miss in cache
- Prefetch block in exclusive state at LL
- But exclusive request reintroduces livelock possibility: use backoff