Logical Protocol to Physical Design

Table of Contents

Logical Protocol to Physical Design

Lock Performance on SGI Challenge

Barriers

Bag of Tricks for Spatial Locality

Logical Protocol Algorithm

Reality

Typical Bus Protocol

Correctness Issues

Preliminary Design Issues

Contention for Cache Tags

Reporting Snoop Results: How?

Reporting Snoop Results: When?

Writebacks

Basic design

Non-Atomic State Transitions

Handling Non-atomicity: Transient States

Serialization

Write completion for SC?

Deadlock, Livelock

Livelock, Starvation

Implementing Atomic Operations

Use cache exclusivity for atomicity

Implementing LL-SC

Multilevel Cache Hierarchies

Maintaining Inclusion

Preserving Inclusion Explicitly

Contention of Cache Tags

Correctness

Home Page: http://www.cs.berkeley.edu/~culler/cs258-s99/

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David E. Culler UC Berkeley CS258 Parallel Computer Architecture Lecture 5