Mini-Instruction Set debate
atomic read-modify-write instructions
- IBM 370: included atomic compare&swap for multiprogramming
- x86: any instruction can be prefixed with a lock modifier
- High-level language advocates want hardware locks/barriers
- but it’s goes against the “RISC” flow,and has other problems
- SPARC: atomic register-memory ops (swap, compare&swap)
- MIPS, IBM Power: no atomic operations but pair of instructions
- load-locked, store-conditional
- later used by PowerPC and DEC Alpha too