Dragon Write-back Update Protocol
4 states
- Exclusive-clean or exclusive (E): I and memory have it
- Shared clean (Sc): I, others, and maybe memory, but I’m not owner
- Shared modified (Sm): I and others but not memory, and I’m the owner
- Sm and Sc can coexist in different caches, with only one Sm
- Modified or dirty (D): I and, noone else
No invalid state
- If in cache, cannot be invalid
- If not present in cache, view as being in not-present or invalid state
New processor events: PrRdMiss, PrWrMiss
- Introduced to specify actions when block not present in cache
New bus transaction: BusUpd
- Broadcasts single word written on bus; updates other relevant caches