Lower-level Protocol Choices
BusRd observed in M state: what transitition to make?
- M ----> I
- M ----> S
- Depends on expectations of access patterns
How does memory know whether or not to supply data on BusRd?
Problem: Read/Write is 2 bus xactions, even if no sharing
- BusRd (I->S) followed by BusRdX or BusUpgr (S->M)
- What happens on sequential programs?