Write-back Caches

• 2 processor operations

  • PrRd, PrWr

• 3 states

  • invalid, valid (clean), modified (dirty)
  • ownership: who supplies block

• 2 bus transactions:

  • read (BusRd), write-back (BusWB)
  • only cache-block transfers

=> treat Valid as “shared” and Modified as “exclusive”

=> introduce one new bus transaction

• read-exclusive: read for purpose of modifying (read-to-own)

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