Sequential Consistency

• Memory operations from a proc become visible (to itself and others) in program order

• There exist a total order, consistent with this partial order - i.e., an interleaving

  • the position at which a write occurs in the hypothetical total order should be the same with respect to all processors

• Sufficient Conditions

  • every process issues mem operations in program order
  • after a write operation is issued, the issuing process waits for the write to complete before issuing next memory operation
  • after a read is issued, the issuing process waits for the read to complete and for the write whose value is being returned to complete (gloabaly) befor issuing its next operation

• How can compilers violate SC? Architectural enhancements?

Previous slide

Next slide

Back to first slide

View graphic version