Systolic Architectures

• VLSI enables inexpensive special-purpose chips

  • Represent algorithms directly by chips connected in regular pattern
  • Replace single processor with array of regular processing elements
  • Orchestrate data flow for high throughput with less memory access

• Different from pipelining
  • Nonlinear array structure, multidirection data flow, each PE may have (small) local instruction and data memory

• SIMD? : each PE may do something different

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