Christopher Celio

Berkeley Architecture Group, ASPIRE Lab
University of California, Berkeley
celio at eecs berkeley edu

About

I am a Computer Architecture Ph.D. candidate in Computer Science at UC Berkeley advised by Krste Asanović and David Patterson. My thesis project has been building the Berkeley Out-of-Order Machine (BOOM), a high-performance RISC-V processor. I received my B.S. and M.Eng degrees in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology.


Download My Resume

My thesis: a free and open processor

BOOM is a synthesizable, parameterized, superscalar out-of-order RISC-V core. My goal is to provide a readable, open-source implementation for use in education, research, and industry. If you would like to use BOOM for your project, I will be happy to help!

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Some of my Github projects...

BOOM processor

A synthesizable, parameterized out-of-order core.

Sodor

A collection of educational RISC-V processors.

ccbench

A collection of memory system micro-benchmarks.

Speckle

A wrapper for the SPEC CPU2006 benchmark suite.


Education

University of California, Berkeley
Berkeley, CA
Pursuing a Doctor of Philosophy degree in Computer Science
(2009-present)
Massachusetts Institute of Technology
Cambridge, MA
Master of Engineering degree in Electrical Engineering and Computer Science
Thesis: Cache Coherence Strategies in a Many-core Processor.
2009
Massachusetts Institute of Technology
Cambridge, MA
Bachelor of Science degree in Electrical Engineering and Computer Science
Minor in Mechanical Engineering
2008

Research

Berkeley Architecture Group, ASPIRE Lab
Berkeley, CA
Researching power-, energy-, and performance-efficient processors. Work includes designing and implementing an industry-competitive, synthesizable out-of-order core for use in heterogeneous multi-core research. Pioneered implementing composable hardware generators using the new hardware construction language Chisel. Work in the past includes designing and implementing vector ISAs as part of an exploration of vector-thread architectures and creating micro-benchmarks to introspect architectural parameters.
(2009-present)
Carbon Research Group, Computer Science & Artificial Intelligence Laboratory (CSAIL)
Cambridge, MA
Evaluated multiple cache coherency schemes using the Graphite 1000-core execution-driven simulator. Also developed the shared memory components of the simulator, which include the DRAM, directories, cache interfacing, and coherence protocols.
2008 - 2009

Publications & Talks

Christopher Celio, Palmer Dabbelt, David A. Patterson, and Krste Asanović, The Renewed Case for the Reduced Instruction Set Computer: Avoiding ISA Bloat with Macro-Op Fusion for RISC-V, Technical Report UCB/EECS-2016-130, EECS Department, University of California, Berkeley, July 2016. arXiv:1607.02318 [cs].
Christopher Celio David A. Patterson, and Krste Asanović, ISA Shootout: Comparing RISC-V, ARM, and x86 on SPECInt 2006, RISC-V Workshop #4, July 2016. Youtube Video.
Donggyu Kim, Adam Izraelevitz, Christopher Celio, Hokeun Kim, Brian Zimmer, Yunsup Lee, Jonathan Bachrach, and Krste Asanović, Strober: Fast and Accurate Sample-Based Energy Simulation for Arbitrary RTL, International Symposium on Computer Architecture (ISCA-2016), Seoul, Korea, June 2016.
Christopher Celio and Rick O'Conner, RISC-V Instruction Set Architecture Update , ORCONF (Bologna), October 2016. Youtube Video, Slides.
Christopher Celio, An update on BOOM and the wider ecosystem (Chisel, FIRRTL, and Rocket-chip) , ORCONF (Bologna), October 2016. Youtube Video, Slides.
Christopher Celio, Documentation for the BOOM processor, Jan 2016. ccelio.github.io/riscv-boom-doc
Christopher Celio, David A. Patterson, and Krste Asanović, The Berkeley Out-of-Order Machine (BOOM): An Industry-Competitive, Synthesizable, Parameterized RISC-V Processor, Technical Report UCB/EECS-2015-167, EECS Department, University of California, Berkeley, June 2015. eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-167.html.
Christopher Celio, David A. Patterson, and Krste Asanović, The Berkeley Out-of-Order Machine (BOOM): An Industry-Competitive, Synthesizable, Parameterized RISC-V Processor, RISC-V Workshop #3, Jan 2016. Youtube Video.
Christopher Celio, David A. Patterson, and Krste Asanović, The Berkeley Out-of-Order Machine (BOOM): Computer Architecture Research Using an Industry-Competitive, Synthesizable, Parameterized RISC-V Processor, RISC-V Workshop #2, June 2015. Youtube Video.
Krste Asanović, Rimas Avizienis, Jonathan Bachrach, Scott Beamer, David Biancolin, Christopher Celio, Henry Cook, Palmer Dabbelt, John Hauser, Adam Izraelevitz, Sagar Karandikar, Benjamin Keller, Donggyu Kim, John Koenig, Yunsup Lee, Eric Love, Martin Maas, Albert Magyar, Howard Mao, Miquel Moreto, Albert Ou, David Patterson, Brian Richards, Colin Schmidt, Stephen Twigg, Huy Vo, and Andrew Waterman, The Rocket Chip Generator, Technical Report UCB/EECS-2016-17, EECS Department, University of California, Berkeley, April 2016.
Christopher Celio, ccbench: Memory System Microbenchmarks, Feb 2014. github.com/ucb-bar/ccbench/wiki
Jason Miller, Harshad Kasture, Charles Gruenwald, Nathan Beckmann, George Kurian, Christopher Celio, Jonathan Eastep, Anant Agarwal, Graphite: A Distributed Parallel Simulator for Large-scale Multicores. The 16th IEEE International Symposium on High-Performance Computer Architecture. Jan 2010.
Christopher Celio, Cache Coherence Strategies in a Many-core Processor. Master's Thesis, Massachusetts Institute of Technology. Sept 2009.

celio at eecs berkeley edu