David Thomas Biancolin

I am a Ph.D student in the Berkeley Architecture Research(BAR) Group, part of the ADEPT and RISE labs at UC Berkeley, where I study computer architecture and VLSI systems design. I am co-advised by Jonathan Bachrach and Krste Asanović.

I received my BASc. in Engineering Science in the Electrical and Computer Engineering Option at the University of Toronto in 2014 (1T3 + PEY).

Email  /  Google Scholar  /  LinkedIn

Research Overview

I'm interested in all things related to the design of VLSI systems, from transistors to CAD. With the end of Moore's law in sight, advances in computing performance and energy effiency must increasingly come from innovations above the process technology. In an effort to make hardware design more accessible, my research studies new FPGA-accelerated simulation tools to help designers verify and validate their systems easily using relatively inexpensive FPGAs-in-the-cloud. See the MIDAS github page for more information. I'm also a contributor to FireSim which uses MIDAS to build cycle-accurate simulators of warehouse-scale computers.

Refereed Publications

DESSERT: Debugging RTL Effectively with State Snapshotting for Error Replays across Trillions of cycles
Donggyu Kim, Chris Celio, Sagar Karandikar, David T. Biancolin, Jonathan Bachrach, Krste Asanović
The International Conference on Field-Programmable Logic and Applications (FPL), 2018

Augmenting MIDAS, DESSERT introduces two mechanisms for bug detection: assertion synthesis and online golden-model checking. Using a techinque we call ganged simulation, DESSERT runs two simulations in parallel, one running ahead of the other, to capture a full-visibility waveform of the design before the bug manifests without simulation slowdown.


FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud
Sagar Karandikar, Howard Mao, Donggyu Kim, David T. Biancolin, Alon Amid, Dayeol Lee, Nathan Pemberton, Emmanuel Amaro, Colin Schmidt, Aditya Chopra, Qijing Huang, Kyle Kovacs, Bora Nikolic, Randy Katz, Jonathan Bachrach, Krste Asanović
International Symposium on Computer Architecture (ISCA), 2018
website / repo / bibtex

FireSim is a cycle-exact, FPGA-accelerated, scale-out computer system simulation platform. The FPGA-hosted components of a FireSim simulator are generated using MIDAS, which transforms Rocket Chip-generated RTL to produce the nodes of the system.


Evaluation of RISC-V RTL with FPGA-Accelerated Simulation
Donggyu Kim, Chris Celio, David T. Biancolin, Jonathan Bachrach, Krste Asanović
Workshop on Computer Architecture Research with RISC-V (CARRV), 2017
bibtex / repo / example

The first public demonstration of MIDAS. MIDAS builds on the work of Strober: it has been ported to Chisel3 and FIRRTL, and produces FPGA-accelerated simulators that are tenfold faster. With the improved speed, we collect energy and performance results from both BOOM and rocket-based processors generated by the Rocket Chip SoC Generator, as they run the SPEC2006int benchmark with reference inputs to completion.


A Hardware Accelerator for Computing an Exact Dot Product
Jack Koenig, David T. Biancolin, Jonathan Bachrach, Krste Asanović
IEEE International Symposium on Computer Arithmetic (ARITH), 2017

We study the implementation of a hardware accelerator, designed in Chisel and hosted in a Rocket Chip-generated SoC, that computes a dot product of IEEE-754 floating-point numbers exactly. The accelerator uses a wide (640 or 4288 bits for single or double-precision respectively) fixed-point representation into which intermediate floating-point products are accumulated.


Fine Grained Interconnect Synthesis
Alex Rodionov, David T. Biancolin, Jonathan Rose
ACM Transactions on Reconfigurable Technology and Systems (TRETS), 2016
TRETS 2016 Best Paper Award Winner
project page / bibtex / repo

Here we present an update of our GENIE paper originally presented at FPGA2015.


Jonathan Bachrach, David T. Biancolin, Austin Buchan, Duncan Haldane and Richard Lin
IEEE/RSJ International Conference on Intelligent Robots and Systems, 2016
bibtex / IEEE Xplore

Commercialization of desktop milling machines has made rapid Printed Circuit Board (PCB) fabrication accessible. Unfortunately, PCB design for embedded and robotic systems is still a tedious and time consuming activity. In this paper, we present a technique, Just In Time Printed Circuit Board (JITPCB) for designing PCB systems at speeds commensurate with the capability of desktop PCB milling machines.


Fine Grained Interconnect Synthesis
Alex Rodionov, David T. Biancolin, Jonathan Rose
ACM/SIGDA International Symposium on Field-Programmable Architectures, 2015
project page / bibtex / repo

We present GENIE, a tool to generate optimized FPGA interconnect at finer granularity of design—just above the pipeline level—than commercial system integration tools like Altera's QSYS.

This paper is subsumed by our 2016 TRETS paper.

Berkeley Technical Reports

The Rocket Chip Generator
Krste Asanović, BAR, and many more still.
Berkeley Technical Report EECS-2016-17
project page / bibtex / repo

Rocket Chip is an open-source System-on-Chip(SoC) design generator that emits synthesizable RTL. It leverages the Chisel hardware construction language to compose a library of sophisticated generators for cores, caches, and interconnects into an integrated SoC.

Shoulders of Giants

My research bootstraps heavily off the work of current and former students of BAR. Many of these projects are open[source] and free to use.


The RISC-V Instruction Set Architecture and Infrastructure
Andrew Waterman, Yunsup Lee, Krste Asanović, David Patterson, and many others.

"RISC-V (pronounced "risk-five") is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now set become a standard open architecture for industry implementations under the governance of the RISC-V Foundation."


The Chisel Hardware Description Language
Jonathan Bachrach and many others, myself included.

"Chisel is an open-source hardware construction language developed at UC Berkeley that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages."

About Me

In my free time I like to climb, hike, and ski. I love to ride bikes, both on the road and on the trail. I used to race XC mountain bikes with the University of Toronto Blues and the Lapdogs Cycling Club. When not outdoors, I enjoy cooking for people and learning new (natural) languages. I maintain this Anki Deck for Berkeley J1A and J1B students.

Appreciate the aesthetic? Wait 'til you see the original.