David Thomas Biancolin

I am a Ph.D student in the Berkeley Architecture Research(BAR) Group, part of the ASPIRE lab at UC Berkeley, where I study computer architecture and VLSI systems design. I am co-advised by Jonathan Bachrach and Krste Asanović.

I received my BASc. in Engineering Science in the Electrical and Computer Engineering Option at the University of Toronto in 2014 (1T3 + PEY).

Email  /  Google Scholar  /  LinkedIn

Research Overview

I'm interested in all things related to the design of VLSI systems, from transistors to CAD. With the end of Moore's law in sight, advances in computing performance and energy effiency must increasingly come from innovations above the process technology. In an effort to make hardware design more accessible, my research studies new FPGA emulation and simulation tools to help designers verify and validate their systems easily using relatively inexpensive commerical off-the-shelf components. See the MIDAS project's webpage for more information.


Fine Grained Interconnect Synthesis
Alex Rodionov, David T. Biancolin, Jonathan Rose
ACM/SIGDA International Symposium on Field-Programmable Architectures, 2015
project page / bibtex / repo

We present GENIE, a tool to generate optimized FPGA interconnect at finer granularity of design – just above the pipeline level – than commerical system integration tools like Altera's QSYS.


Jonathan Bachrach, David T. Biancolin, Austin Buchan, Duncan Haldane and Richard Lin
IEEE/RSJ International Conference on Intelligent Robots and Systems, 2016

Commercialization of desktop milling machines has made rapid Printed Circuit Board (PCB) fabrication accessible. Unfortunately, PCB design for embedded and robotic systems is still a tedious and time consuming activity. In this paper, we present a technique, Just In Time Printed Circuit Board (JITPCB) for designing PCB systems at speeds commensurate with the capability of desktop PCB milling machines.

Berkeley Technical Reports

The Rocket Chip Generator
Krste Asanović, BAR, and many more still.
Berkeley Technical Report EECS-2016-17
project page / bibtex / repo

Rocket Chip is an open-source System-on-Chip(SoC) design generator that emits synthesizable RTL. It leverages the Chisel hardware construction language to compose a library of sophisticated generators for cores, caches, and interconnects into an integrated SoC.

Shoulders of Giants

My research bootstraps heavily off the work of current and former students of BAR. Many of these projects are open[source] and free to use.


The RISC-V Instruction Set Architecture and Infrastructure
Andrew Waterman, Yunsup Lee, Krste Asanović, David Patterson, and many others.

"RISC-V (pronounced "risk-five") is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now set become a standard open architecture for industry implementations under the governance of the RISC-V Foundation."


The Chisel Hardware Description Language
Jonathan Bachrach and many others, myself included.

"Chisel is an open-source hardware construction language developed at UC Berkeley that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages."

Appreciate the aesthetic? Wait 'til you see the original.