EECS 290A

Advanced Methods in Logic Synthesis and Equivalence Checking 

 

Overview 

Logic synthesis and equivalence checking enable development of CAD tools for design and verification of computer hardware and software. The connection between these two fields is becoming increasingly tighter, especially when combinational methods reach their limits and begin to be supplemented by sequential methods.

In this course, we will illustrate how ideas from the verification community have led to a kind of “rewriting the book for logic synthesis”, which is embodied in a synthesis and verification tool, called ABC being developed at Berkeley. The flow of ideas is also bidirectional, leading to our belief that research and development in one area should go hand-in-hand with the other. This is especially important for industry where traditionally, synthesis and verification are done by two different groups, often at different sites.

Advancing logic synthesis and equivalence checking has the goal of increasing speed, scalability, verifiability, and superior results over classical methods. Recently focus has moved to the sequential domain where new results are leading to greater acceptance of sequential operations such as retiming, register correspondence, and use of approximate unreachable states. Examples illustrating this synergy and new developments include:

  • unifying representation (sequential AIGs),
  • cut/window-based techniques ensuring scalability,
  • assume-then-prove paradigm through simulations and SAT,
  • finding good approximate solutions using interpolation,
  • recording and use of a history of synthesis transformations.

The course will consist of one 2-hour meeting a week.

We will start with in-depth studies of core computations (combinational and sequential AIG packages, cut enumeration, window computations, truth table manipulations, retiming, and simulation methods), which are implemented in ABC as tool-kit packages. The efficiency of these methods is critical to enable a variety of different applications.

We will show how almost all of the classical synthesis methods (kerneling, use of SOPs and ESPRESSSO, Boolean (SIS) networks, computation of don’t cares, etc.) can be replaced by newer, faster, more scalable methods, which because of their speed, can be repeated many times, leading to results that are superior to classical synthesis. In the last part of the course, we will look at sequential synthesis and related verification problems.