EECS 290N

Equivalence Checking

Overview

The problem of equivalence checking is that of proving that two different versions of something, compute the same thing. This course will explore this subject in depth. The course will consist of one 2-hour meeting each week in the form of a study seminar. After a few weeks of introductions to the subject, each student will be assigned a recent paper in the field that he/she will present in class and lead a discussion. The course will focus on building up a state-of-the-art expertise of the participants. There will be a common project in the course on the implementation of a sequential equivalence checker (SEC) which can beat the best one currently in existence. The grade for the course will be based on the student’s participation in class and on the project.

In VLSI design, equivalence checking comes in two forms, combinational and sequential. In particular, combinational equivalence checking (CEC) has seen great advances in recent years, with several successful startups appearing and being bought out. At Berkeley, we have recently developed a CEC engine, which we think represents the state-of-the-art, as confirmed by its application in an industrial startup as well as in software synthesis. Sequential equivalence checking (SEC) is harder.

The problem is: given two FSMs and a pair of initial states, prove that the two machines starting from their respective initial states produce identical sequences of outputs for any given sequence of inputs. While CEC is co-NP-complete, SEC is PSPACE-complete. However, in both cases, practical instances of these problems share a lot of common structures, which can be exploited, making the problems much easier in practice. Our CEC engine exploits this in several ways that may carry over to SEC, and this will be the beginning basis for the class project. Additionally, we will address the question of “checking the checker” by generating a proof-of-equivalence sequence, which can be easily verified by a simple independent tool.