1. Introduction
2. Combinational versus sequential
a. registers and transparent latches
b. generic state reachability
c. when is a cyclic circuit combinational
d. synthesis of cyclic circuits
e. timing analysis of cyclic combinational circuits
3. Asynchronous design
a. general overview
b. clockless and de-synchronized designs
c. DI encoding methods
d. bundled delay methods
e. at-speed delay testing
f. Globally Asynchronous Locally Synchronous (GALS) designs
g. Latency Insensitive Design
4. Clocking networks
a. Topologies
b. Accounting for parametric variations
5. FSM manipulations
a. State-based
i. reachability analysis (basics in 219B)
ii. sequential flexibility and windowing
iii. re-encoding
iv. state minimization
b. Structure-based
i. Retiming and re-synthesis (Basics in 219B)
1. initialization sequences
2. peripheral retiming and negative latches
3. inherent power of retiming and resynthesis
4. retiming, clock skewing, and placement
5. retiming in technology mapping
6. high level retiming
ii. sequential testing and redundancy removal
iii. seq. syn. w/o state space enumeration
6. Sequential equivalence checking between two FSMs
a. comparison of 3 methods
b. use of SAT and FRAIGs
c. interpolation
7. Formal Verification
a. bounded model checking (see 219B)
b. temporal logic
c. language containment
d. interpolation
e. functional dependence
8. Other topics (which may be interleaved with the above)
a. verifying clock schedules (Szymanski-Shenoy)
b. process variability in Deep Sub-Micron (DSM)
c. statistical timing methods
d. false paths
e. delay fault testing
f. complete flexibility in comb. and seq. synthesis
g. flexibility from information flow (SPFDs)
h. non-deterministic multi-valued networks
i. advanced technology mapping
i. gain based
ii. wavefront
iii. supergates
iv. area recovery – area flow
v. choices and choice node