The previous work [1] proposes a way to perform sequential optimization using recursive learning across latch boundaries. The goal of this project is to investigate possible extensions of this work, trying to get deeper understanding of the relationship of the algorithm with other sequential optimization techniques. Another goal is to develop an efficient implementation of this method in MVSIS.
[1] A. Mehrotra, S. Qadeer, V. Singhal, R. K Brayton, A. L. Sangiovanni-Vincentelli, A. Aziz. Sequential optimization without state space exploration. Proc. ICCAD ‘97, pp. 208-215.
It was shown [1] that unit-delay circuits (circuits composed of combinational blocks with equal delay) allow for a reduction in the complexity of the retiming algorithm. This project explores the applicability of these results to the retiming of sequential circuits represented by AIGs [2] with latches. The goal is to improve the computational efficiency of retiming and test the results on large circuits.
[1] M. C. Papaefthymiou, Understanding retiming through maximum average-delay cycles. Mathematical Systems Theory, 27, 1994, pp. 65-84.
[2] A. Mishchenko, S. Chatterjee, R. Jiang, R. Brayton. FRAIGs: A Unifying Representation for Logic Synthesis and Verification. Submitted to DAC ’05.
A study [1] has shown that the quality of results achieved by iterating retiming and technology mapping for FPGAs can be improved by integrating these transformations into one. This project will develop a similar technique for ASIC mapping [2] and study its impact on the mapping quality.
[1] J. Cong and C. Wu, Optimal FPGA Mapping and Retiming with Efficient Initial State Computation, IEEE TCAD, vol. 18(11), pp 1595 -1607, Nov. 1999.
[2] A. Mishchenko, S. Chatterjee, R. Brayton, X. Wang, T. Kam. Technology Mapping with Boolean Matching, Supergates and Choices. Submitted to DAC ’05.
This is an experimental study of the efficiency of random simulation for stuck-at fault detection in sequential circuits. To detect a fault at a given location, we compare a faulty circuit with the original one. For this we construct functionally-reduced AIG [1] for the miter circuit, and determine how many stuck-at faults in the combinational logic can be detected by (a) random simulation, (b) bounded equivalence checking (unfolding of the circuit for a given length, while trying different unfolding length: 10, 50, 100, etc), and (c) how many faults cannot be detected by (a) and (b). It will be interesting to know the exact numbers for a selection of practical benchmarks. The result of this experiment will help answer the question whether bounded equivalence checking is a good method to generate tests for stuck-at faults in sequential circuits.
[1] A. Mishchenko, S. Chatterjee, R. Jiang, R. Brayton. FRAIGs: A Unifying Representation for Logic Synthesis and Verification. Submitted to DAC ’05.
In optimizing large networks, a transformation cannot always be applied to the network as a whole. A technique known as windowing is introduced to remedy the situation. This technique consists in scanning the network with a “window” of the fixed size. Modifications are applied only to the nodes inside the current window, while the nodes outside the window remain unchanged. In fact, the window itself would act as its own specification, so that the external I/O outside the window is identical with what was there before. However, inside the window, we may change the components.
This project will focus on studying the available windowing schemes for combinational networks and extending them to work for networks with latches. Several applications will be implemented and tested to show the impact of windowing on the runtime/quality trade-off. The applications may include reachability analysis, reencoding using the set of unreachable states, computation of combinational don’t-cares due to unreachable and equivalence states using methods similar to [1].
[1] A. Mishchenko, R. Brayton. SAT-based complete don’t-care computation for network optimization. Proc. IWLS ’04.
(
Since Binary Decision Diagrams (BDDs) have been proposed in late 50s, several applications have been studied, where this data structure can be successfully applied. In formal verification and logic synthesis BDDs have become the state-of-the-art for function representation and manipulation. BDDs have also been studied in logic synthesis, since they allow for combining circuit synthesis and technology mapping. Recently, there is a renewed interest in multiplexor based design styles, since often multiplexor nodes can be realized at very low cost (as e.g. Pass Transistor Logic (PTL)). In addition, these techniques consider layout aspects during the synthesis step and by this guarantee high design quality.
One of the most important steps during circuit design is the testability of the netlist. Multiplexor circuits derived from BDDs have been studied intensively under various fault models. Recently, a new technique has been presented that guarantees full testability of a circuit derived from a BDD description under the stuck-at fault model and the robust path-delay fault model. The size of the circuit is directly proportional to the given BDD size.
The goal of this project is to generalize the techniques [1] to work for sequential circuits, i.e. circuits that are not full-scan. The problem can be studied from a theoretical point of view or by an experimental study in the MVSIS environment.
[1] R. Drechsler, J. Shi, G. Fey. Synthesis of Fully Testable Circuits from BDDs. IEEE Trans. CAD, Vol. 23(3), March 2004, pp. 440-443.
(
Two sequential netlists are available, one of them derived from the other by a phase assignment of the latches. The inverters are collapsed and the logic functions are restructured. The correspondence of latches in the two netlists is known. The problem is to check if the two designs are indeed equivalent under some phase assignment. A general-case sequential equivalence checking method can be used, but the question is if there exists a more efficient method applicable to the special type of the netlist after phase assignment.
Given two finite state machines, the sequential equivalence checking problem asks if they are indistinguishable from their output responses on any input sequences. Checking the equivalence of two finite state machines is of great importance in ensuring the correctness of hardware design and optimization. A traditional solution to this problem is based on binary decision diagrams (BDDs). Extensively studied for over a decade, BDD-based approaches are still not scalable to verify large systems (with hundreds or thousands of registers). To overcome this limitation, researchers have been considering alternative new data structures. Recent advances of SAT-solvers bring SAT formulation to one of the main streams in formal verification. However, most of the prior work on this subject aimed at general model checking. Since sequential equivalence checking is a very specific and practically important problem in design verification, presumably specialized algorithms (e.g. exploiting similarities of circuit structures) may further improve verification performance. This project studies the most recent development of SAT-based model checking, and applies it to the sequential equivalence checking problem. Students working on this project will get familiar with the verification area, and gain programming experience with an advanced SAT-solver.
[1] K.L. McMillan. Interpolation and SAT-based model checking, Proc. CAV'03, LNCS 2725, Springer, 2003, pp. 1-13.
Resubstitution is a transformation widely used to restructure combinational circuits. It consists in changing the inputs of a node in such a way that the local function of the node is simplified, some of the old inputs are possibly dropped, some of the new inputs are possibly added, while the global function of the node remains unchanged. A procedure can be developed for checking the condition when resubstitution is possible. The procedure can be implemented using BDDs, or using Boolean satisfiability with random simulation as a pre-filter.
This project will explore extensions of the notion of resubstitution for sequential circuits. The idea of one such extension comes from the following observation. If we consider two uninitialized consecutive time-frames of a sequential circuits as one combinational circuit, some nodes in the first frame can be resubstituted into the second frame. Going back to the original circuit, this transformation can be interpreted as adding a new latch to the circuit and reexpressing the logic function of a node in terms of the new latch. This reexpression may lead to simplification of the node’s local function, or to dropping fanins of the node, which may result in making redundant some latches of the original circuit.
The goal of this project is to develop a theory supporting resubstitution in sequential circuits and implement an experimental command in the MVSIS environment, which will be applicable to large sequential circuits.
Last year Ruth Wang’s project in EE290N was to try to use flexibility to modify a circuit to that it would work in the presence of a few errors that could happen if Vdd is reduced to save power. The experiments were limited to a few inputs from a correcting sub-circuit C, which was synthesized using the sequential flexibility computation of the unknown component problem. The synthesis part of her project was very rudimentary and not optimal, but the project was merely a feasibility study. In the problem addressed, there is a deterministic fixed part F interacting with an unknown component C. A specification S is also deterministic and provides the desired behavior of the combined interacting parts. Using S and F, the complete flexibility of the component C was computed using computations available in the MVSIS environment. The solution, X, called the complete flexibility of C, is in general a non-deterministic FSM. If it is well-defined (for every input there is an output and next state), then an implementation for C exists. The fixed part F had a particular circuit structure, and SPICE simulations were used to determine ways F could fail as Vdd is decreased. A chapter of Ruth’s master’s thesis is available for the details of this experiment. The mechanism used in this study for correcting F was through additional inputs from C, which would modify the behavior of F.
We can think of the reduced Vdd as just an example of a type of process or environmental variability. Other parameters might be Leff, Vth, temp, etc. Also in reality, the part F may or may not fail under some variations of the parameters, which means its behavior can be viewed as non-deterministic. We want a mechanism, which corrects F when it fails and leaves the circuit alone when there is no failure. The complete flexibility can still be computed in a very similar way using MVSIS, but because of this additional requirement, the possibility of the existence of a solution is reduced. This implies the invention of stronger correction mechanisms applied to F and possibly some feedback from F to C indicating something about its possible failing.
If a correcting circuit exists, this implies that what has been built is a combined circuit F*C, implementing S. This circuit is redundant because F itself implements S. The redundancy is there to make the circuit more rugged w.r.t. parameter variations. A larger view is that this project is concerned with using sequential flexibility to construct a more rugged circuit that is less vulnerable to process and environmental variations.
Ruth’s master’s thesis also contains other chapters which give a good introduction to such problems.
The student would get familiar with Ruth’s thesis, the literature on computing sequential flexibility, and explore additional methods for observing and correcting a failing circuit to make it more rugged. He/she would work through some examples (Ruth’s thesis contains one) to derive X and optimize it. A long-term research direction (not part of the expected project result) is to find a way of building redundant circuits (circuits containing an error-correcting mechanism) which is more efficient than, for example, triple redundancy and majority polling.