The sequential nature of a design involves the use of storage elements to capture sequences of events (states), which can be clocked or not. Although there has been much research in sequential optimization, little has found its way into commercial offerings. This course will review state-of-the-art methods to identify their potential for further development and inclusion in future synthesis systems. A necessary part of synthesis is the ability to verify what has been synthesized. Two aspects of formal verification will be covered, equivalence checking and property verification, both of which have seen significant progress recently.