Reverse Engineering Digital Circuits Using Structural and Functional Analyses
Pramod Subramanyan, Nestan Tsiskaridze, Wenchao Li, Adria Gascon, Wei Yang Tan, Ashish Tiwari, Natarajan Shankar, Sanjit A. Seshia, and Sharad Malik. Reverse Engineering Digital Circuits Using Structural and Functional Analyses. IEEE Transactions on Emerging Topics in Computing, 2(1):63–80, March 2014.
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Abstract
Integrated circuits (ICs) are now designed and fabricated in a globalized multivendor environment making them vulnerable to malicious design changes, the insertion of hardware Trojans/malware, and intellectual property (IP) theft. Algorithmic reverse engineering of digital circuits can mitigate these concerns by enabling analysts to detect malicious hardware, verify the integrity of ICs, and detect IP violations. In this paper, we present a set of algorithms for the reverse engineering of digital circuits starting from an unstructured netlist and resulting in a high-level netlist with components such as register files, counters, adders, and subtractors. Our techniques require no manual intervention and experiments show that they determine the functionality of $>45$% and up to $93$% of the gates in each of the test circuits that we examine. We also demonstrate that our algorithms are scalable to real designs by experimenting with a very large, highly-optimized system-on-chip (SOC) design with over 375,000 combinational elements. Our inference algorithms cover $68$% of the gates in this SOC. We also demonstrate that our algorithms are effective in aiding a human analyst to detect hardware Trojans in an unstructured netlist.
BibTeX
@ARTICLE{subramanyan-tetc14,
author={Subramanyan, Pramod and Tsiskaridze, Nestan and Li, Wenchao and Gascon, Adria and Tan, Wei Yang and Tiwari, Ashish and Shankar, Natarajan and Seshia, Sanjit A. and Malik, Sharad},
journal={IEEE Transactions on Emerging Topics in Computing},
title={Reverse Engineering Digital Circuits Using Structural and Functional Analyses},
year={2014},
month={March},
volume={2},
number={1},
pages={63--80},
abstract={Integrated circuits (ICs) are now designed and fabricated in a globalized multivendor environment
making them vulnerable to malicious design changes, the insertion of hardware Trojans/malware,
and intellectual property (IP) theft. Algorithmic reverse engineering of digital circuits can mitigate these
concerns by enabling analysts to detect malicious hardware, verify the integrity of ICs, and detect
IP violations. In this paper, we present a set of algorithms for the reverse engineering of digital circuits
starting from an unstructured netlist and resulting in a high-level netlist with components such
as register files, counters, adders, and subtractors. Our techniques require no manual intervention and
experiments show that they determine the functionality of $>45$\% and up to $93$\% of the gates in each of
the test circuits that we examine. We also demonstrate that our algorithms are scalable to real designs
by experimenting with a very large, highly-optimized system-on-chip (SOC) design with over 375,000
combinational elements. Our inference algorithms cover $68$\% of the gates in this SOC. We also demonstrate
that our algorithms are effective in aiding a human analyst to detect hardware Trojans in an unstructured
netlist.},
}