DARPA VLSI Project Review

Richard Newton

University of California

DARPA VLSI Project Review

Berkeley CAD Group Emphasis

Simplified Model of Design

Evolution of Electronic Design Technology: 1970s

Evolution of Electronic Design Technology: Early 1980s

Evolution of Electronic Design Technology: Mid 1980s

Physical Design of VLSI Circuits

CAD Needs for System Design

CAD Needs for System Design

CAD Needs for System Design

CAD Needs for System Design

I/O Pin Requirements

Multi-Chip Modules

CAD Issues for Multi-Chip Modules

DARPA Projects Technology Modelling & Analysis

DARPA Projects ASICS and Multi-Chip Modules

Evolution of Electronic Design Technology: Late 1980s

Application of Logic Synthesis

Role of Don't-Cares in Logic Synthesis

Role of Don't-Cares in Logic Synthesis

Role of Don't-Cares in Logic Synthesis

Optimality & Redundancy in Combinational Logic

DARPA Projects Combinational Synthesis

State Assignment

Synthesis-Directed Sequential Test

Test Generation for Finite-State Machines

Synthesis Procedure for Fully-Testable Non-Scan Finite-State Machine

Synthesis Procedure for Fully-Testable Non-Scan Finite-State Machines

Cascaded Finite-State Machines

Coupled Finite-State Machines

Example FSMs

Constrained State Assignment (single cones)

Constrained State Assignment (single cones)

Effect of Gate Duplication in Standard-Cell Layout

Use of Extended Don't-Care Set to Guarantee Testability

Example Finite-State Machine with Fault d

Example Finite-State Machine Effect of Fault d

Example Finite-State Machine with Fault g

Example Finite-State Machine Effect of Fault g

Example FSMs

Results of Synthesis Procedure

Results Using Extended Don't-Care Sets During Synthesis

Synthesis-Directed Sequential Test

DARPA Projects Sequential Synthesis

Evolution of Electronic Design Technology: Early 1990s

Evolution of Electronic Design Technology: Mid 1990s

Design Specification and Verification

Behavioral Synthesis

Context for Behavioral Synthesis

Representing the Synthesis Problem: The Conventional Approach

Representing the Synthesis Problem: An Alternative Approach

"I synthesize from C" or "I synthesize from VHDL"

HCode: The Software Analogy Intermediate Form

Simple Dataflow Description

Behavior and Structure

Behavior and Structure: Two Faces of the Same Coin

HCode: The Software Analogy Abstract Datatype Approach to Consistency

Data and Control

Ella: A Hardware Design & Description Language

Ella: A Hardware Design & Description Language

An Alternate View of Synthesis

An Alternate View of Synthesis

An Alternate View of Synthesis

An Alternate View of Synthesis

HCode Datatypes

An Alternate View of Synthesis

Two Approaches to Combinational and Sequential Optimization

An Alternate View of Synthesis: Implications

DARPA Projects Design Verification

Synthesis-Directed High-Level Simulation

DARPA Projects Behavioral Synthesis

Representing Time for Behavioral Description

Why Should Time be Discrete?

Representing Time for Behavioral Descriptions

HCode Temporal Model

Evolution of Electronic Design Technology: Late 1990s

DARPA Projects Analog

What is a "CAD Framework?"

What is a "CAD Framework?"

How do you recognize a Good One when you see it?

Aspects of Framework Development

The Translator- Based Approach: A Tool-Centric View of Design

Major Features of a CAD Framework Today: An Integration-Centric View of Design

Major Features of a CAD Framework Today

Major Features of a CAD Framework Today

User Interface Facilities Today

"CAD- Specific" Services Provided Today

Versions, Alternatives, and Configurations

Versions, Alternatives, and Configurations

Design-Flow Management

Engineering vs. Scientific Problems

Traditional Approach to Software Development

A Successful Model for Engineering Software Development

Approaches to Engineering Software Development

Berkeley Framework Users Today

Berkeley Framework Users Today

Framework Development at Berkeley: Towards Design-Centric Frameworks

Framework Development at Berkeley

Berkeley CAD Group Emphasis