Andrew R. Neureuther, 509 Cory Hall, Version 01/11/05
Conexant Distinguished Professor,
Electrical Engineering and Computer Sciences
UCB TCAD PROCESS TECHNOLOGY NOTES or (PTN Direct)
LAVA (remote simulation) or (LAVA Direct)
CLASSES TEACHING or (EE 243 Direct)
ADMINISTRATION CONTACT INFORMATION RESEARCH
RECENT TALK BIO/PUBS LITHOGRAPHY WEB SITES
Tentative Office Hours
11 M, 1 Tu, 2 F
Tentative Weekly Schedule (Matrix Form in PDF).
CLASSES SPRING 06:
EE 243 Advanced IC Processing and Layout, Tu, Th 11-12:30, 299 Cory
EE 298-10 Integrated Circuit Technology Seminar, F 11, Room 531 Cory
EECS 298-39 Feature Level Compensation and Control Seminar, M 2, Wang Room 531 Cory
EECS 298-12 Solid State Technology and Devices Seminar, F 1, Hogan Room 535 Cory
Phone/Fax: Tel. 510-642-4590, Fax. 510-642-2739
Address: Professor Andrew R. Neureuther, Dept. EECS 231 Cory Hall,
University of California, Berkeley, CA 94720-1770,Research Services Assistant: Charlotte Jones, 510-643-2834, cmjones@eecs (mailto)
Research Services Officer: FLCC Ellen Lenzi, 510-643-9665, lenzi@eecs (mailto)
Research Services Officer: SRC/DARPA Carol Zalon, 510-642-xxxx, zalon@eecs (mailto)
Faculty PI, U.C. Discovery,
Feature Level Compensation and Control Program
EE ABET Coordinator,
Faculty Coordinator, EECS Internship Program
Faculty Coordinator, SUPERB (Summer Undergraduate Program, CoE)
Member, Applied Science and Technology, Graduate Group
TEACHING:Spring 2005, I will be teaching the 3 unit graduate course EE 243 Advanced IC Procesing and Layout. This course emphasizes the physical principles and mathematical models used to characterize fabrication and inspection processes in microfabrication technology. It begins with a brief overview of the CMOS fabrication process flow, its key technology elements, and the issues that limit these processes. We then turn to the key process steps and spend about 5 weeks on mechanisms and models for oxidation, diffusion, implantation, CVD and dry etching. This is followed by 2 weeks on statistical process control (SPC) and design of experiments (DOE) as used to support high yield manufacturing. At this point there is a midterm exam. We then spend 4 weeks on developing advanced models for optical image formation, resist response, defect printability, inspection and next generation electron-beam and EUV exposures systems. Two weeks are then spent on interconnect processes and integration process flow/layout. The last week is extensions to nanfabrication and oral project reports. There is one review lecture before the final.
UCB TCAD PROCESS TECHNOLOGY NOTES: (go to PTN for more information)
This is an evolving mini-library of snipits of materials on
physically based model for characterizing microfabrication technology.
It tends emphasize
optical lithography as this is the main interest of the TCAD Group at
The purpose is to make available globally two types of information of likely practical use in microfabrication.
Materials that supplement existing textbooks on process technology and might be used in classes.
Information on concepts and results from research that likely contribute to the practice of microfabrication.
My research interests are photolithography and integrated circuit process technology simulation. You can view recent results from the SAMPLE Technology CAD Group.
LAVA Remote Simulation: (go to LAVA for more information)
Analysis through Virtual Access web site facilitates remote
simulation using TCAD
tools from the SAMPLE Group. This includes SPLAT, SAMPLE, SIMPL,
PBODY-BEAM and SAMPLE3D. There are a number of application-oriented
applets for user convenience. It is also possible to remotely launch
and the Pattern Matcher.
The research of my group is sponsored in part under the Feature Level Compensation and Control project in the State of California and Industry U.C. Discovery program. It is also supported in part under the Network for Advanced Lithography sponsored by DARPA/SRC.
LITHOGRAPHY WEB SITES: (go to LAVA for additional information on TCAD)