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CS252: Homework Assignment #2
Due Wednesday, December 6th
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The
homework assignment for Wednesday, 11/17 for CS 252 is to do the following
exercises from the Computer Architecture textbook:
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5.4,5.5
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5.6 (note: the reference in the problem to page 401 is incorrect;
the correct Example can be found on pages 403-404)
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5.7,5.9,5.10,5.20 (please limit your answer to one or two paragraphs)
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6.5,6.6,6.10
Additional Question: Ex 1
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Assume that we have a bus-based shared-memory multiprocessor using the
MESI protocol. Each processor in the system is identical, and the
following information applies to each processor in the system individually:
25% of the instructions executed by each processor are loads or stores
(instructions are 32 bits wide). Of these loads and stores, on average
75% are reads to private data, 15% are writes to private data, 8% are reads
to shared data, and 2% are writes to shared data. Each processor
has a single-level split instruction/data cache. The instruction
cache is 16KB, two-way associative, and has 32 byte lines. The data
cache is 16KB, direct mapped, and also has 32 byte lines. The hit
rates in the caches are as follows: 97.5% for private data, 95% for shared
data, and 99% for instructions. Cache hit time is one cycle for both
caches.
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The SMP system bus has separate address and data busses, with 64 data
lines and 32 address lines. The bus is atomic (not split-transaction),
so the address and data busses can be treated as a single bus with respect
to negotiation. The bus is clocked at 1/2 the speed of the processor.
For reads, memory responds with data 10 bus cycles after being presented
the address, and supplies one block of data per bus cycle after that.
For writes, both address and data are presented to memory at the same time.
Thus, a single-word write consumes 1 bus cycle, while a 32-byte write consumes
four cycles. Assume all requests are satisfied by the memory system,
not by other caches. The processor CPI is 2.5 before considering
memory penalties.
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Assume that there is only a single processor. What is the CPI that
the processor sees if the caches are write-through with a write-allocate
strategy?
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What is the bus utilization of a single processor? Hint:
use your answer to (1).
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How many of these processors can the bus support before it saturates?
Ignore bus contention and coherence messages received from other processors.
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What is the effective CPI if the caches are write-back (and write-allocate)?
Assume that the probability of having to replace a dirty block in the cache
on a miss is 30%.
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Now how many of these processors can the bus support before it saturates?
Again ignore bus contention and coherence messages received from other
processors.
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Finally, assuming that the bus can be treated as a memoryless queuing system,
what is the effective CPI seen by the processors in the multiprocessor
configuration of (5)? note that this CPI will be bigger than that
of (3) because of queuing effects.
If any problems are unclear or missing assumptions, please send email to
Mark Whitney and/or Prof. Kubiatowicz, and we will try to clarify them
ASAP.
These exercises should be done in
pairs, but both need to understand whole assignment. One set of solutions
should be turned in with both names at the top.
Study groups are encouraged, but
pairs should do their own work.
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Maintained by John Kubiatowicz (kubitron@cs.berkeley.edu)
Last
modified November 22, 2000