Multilevel Cache Hierarchies
Independent snoop hardware for each level?
- processor pins for shared bus
- contention for processor cache access ?
Snoop only at L2 and propagate relevant transactions
Inclusion property
(1) contents L1 is a subset of L
(2) any block in modified state in L1 is in modified state in L2
1 => all transactions relavant to L1 are relavant to L2
2 => on BusRd L2 can wave off memory access and inform L1