Improved Hardware Primitives: LL-SC
Goals:
- Test with reads
- Failed read-modify-write attempts don’t generate invalidations
- Nice if single primitive can implement range of r-m-w operations
Load-Locked (or -linked), Store-Conditional
- LL reads variable into register
- Follow with arbitrary instructions to manipulate its value
- SC tries to store back to location
- succeed if and only if no other write to the variable since this processor’s LL
- indicated by condition codes;
If SC succeeds, all three steps happened atomically
If fails, doesn’t write or generate invalidations