Accounting for Wire Delays and Cross Talk

1. Optimizing dominant time constants in RC circuits
2. Wire planning instead of floor planning
3. Clustering and technology mapping to aleviate wire delays
4. Creating tight islands of logic computation - using large libraries and advanced technology mapping.
5. On-the-fly construction of highly compact cells - possibly using pass transistor, domino logic or cascode logic.
6. Iterating synthesis and layout - approximating/abstracting the layout process (1. DAC 1994, p327 - Methodology and Algorithms for Post-placement Delay Optimization 2. book - Circuits, Interconnections, and Packaging for VLSI - H.B. Bakoglu)
7. Controlling noise problems in deep submicron (1. Bakoglu's book 2. Ken Shepard and Vinod Narayanan - (tutorial-ICCAD 96))
8. Using advanced delay models and the false path problem
9. New methods for on-chip communication - e.g. a) replacing buses with switching networks or b) using small-swing signalling to speed communication or c) introducing local high speed clocks with flexible intercomponent communication d) locally synchronous - globally asynchronous synthesis or e) synthesis of externally synchronous internally asynchronous circuits
10. simultaneous buffer and wire optimization (work by Jason Cong and Larry Pillagi)
11. transistor sizing (1. TLOS - Alfred Dunlap (appeared in TCAD, DAC) 2. Convex Optimization - Sachin Sapetnekar (TCAD a couple of years ago))