4.1.1 Two-Level (1982 – 1987)
4.1.2 Multi-level –
Technology Independent (1981 – 2001)
4.1.3
Incremental Re-Synthesis – Engineering Change (1991 – 1997)
4.1.4
BDDs, SAT, Covering Problems etc. (1989 – 2002)
4.1.5
Technology Mapping and FPGA Synthesis (1980 – 2000)
4.1.6
Delay Optimization (1988 – 1994)
4.1.7
Flexibilities – Don’t Cares and SPFDs (1986 – 2002)
4.1.8
Asynchronous (1990 – 1994)
4.1.9
Multi-Valued Logic (1990 – 2002)
4.2.1
State Assignment, State Minimization, and Encoding (1984 – 1997)
4.2.2
Retiming (1990 – 2001)
4.2.3
Sequential Flexibility (1993 – 2002)
4.2.4
General (1990 – 2002)
6.1
Testing (1990 – 1997)
6.2 Equivalence Checking
(1988 – 2002)
6.3 Model Checking (1991 –
2002)
1.
R.K. Brayton, "On the Asymptotic Behavior of the
Number of Trials Necessary to Complete a Set with Random Selection," Ph.D.
Thesis, M.I.T., September 1961 and J. of Mathematical Analysis and Applications
7, 1, pp. 31-61, August 1963. PhD Thesis
2.
R.K. Brayton and W.L. Miranker, "A Stability Theory
for Nonlinear Mixed Initial Boundary Value Problems," RC-1021, IBM
Research Center, Yorktown Heights, NY, August 1963 and Arch. Ratl. Mech. and
Anal. 17, 5, 358-376, December 1964.
3.
R.K. Brayton, F. Gustavson and W. Liniger,
"Numerical Analysis of the Transient Behavior of a Transistor
Circuit," RC-1193 IBM Research Center, Yorktown Heights, NY, May 1964 and
IBM Journal of Research and Development 10, 4, 292-299, July 1966.
4.
R.K. Brayton, "Bifurcation of Periodic Solutions in
a Nonlinear Difference- Differential Equation," RC 1427, IBM Research
Center, Yorktown Heights, NY, June 1965 and Applications of Mathematics, XXIV,
No. 3, pp. 215-224, October 1966.
5.
R.K. Brayton and R.A. Willoughby, "On the Numerical
Integration of a Symmetric System of Difference-Differential Equations of
Neutral Type," RC 1507, IBM Research Center, Yorktown Heights, NY,
December 1965 and Journal of Mathematical Analysis and Applications, 18,
182-189, 1967.
6.
R.K. Brayton, "On the Bifurcation of Periodic
Solutions in Nonlinear Difference-Differential Equations of Neutral Type,"
Proceedings of Symposium on Differential Equations and Dynamical Systems,
Puerto Rico, Academic Press, 1967.
7.
R.K. Brayton, Fred G. Gustavson and Ralph A. Willoughby,
"Some Results on Space Matrices," Sparse Matrix Proceedings,
Yorktown, NY, pp. 43-58, September 1968.
8.
R.K. Brayton, F. G. Gustavson and R. A. Willoughby,
"Some Results on Sparse Matrices," RC 2332, February 1969, IBM
Research Center, Yorktown Heights, NY, Math. Comp. 24, 112, pp. 937-954,
October 1970.
9.
R.K. Brayton, "Necessary and Sufficient Conditions
for Bounded Global Stability of Certain Nonlinear Systems," RC 2623, IBM
Research Center, Yorktown Heights, NY, September 1969, Applications of
Mathematics, pp. 237-244, July 1971.
10.
R.K. Brayton, "Totally Unimodular Matrices which are
Path-Branch Incidence Matrices of Directed Trees," RC-2849, IBM Research
Center, Yorktown Heights, NY, April 1970.
11.
R.K. Brayton, "The Use of the ASTAP Language for
General Model Simulation," IBM Technical Memorandum, June 1970.
12.
R.K. Brayton, "Necessary and Sufficient Conditions
for Bounded Global Stability of Certain Nonlinear Systems," Proceedings
Kyoto International Conference on Circuit and Systems, Kyoto, Japan, September
1970.
13.
R.K. Brayton, F.G. Gustavson and G.D. Hachtel , “A New
Efficient Algorithm for Solving Differential-Algebraic Systems Using Implicit
Backward Differentiation Formulae”, RC-3381, IBM Research Center, Yorktown
Heights, NY, June 1971; Proceedings of IEEE, pp. 98-108, January 1972.
14.
W.L. Miranker and R.K. Brayton, "Notes for a Short
Course in Mathematical Modeling and Computer Techniques," NSF Chautauqua
Short Courses for College Teachers, 1972.
15.
R.K. Brayton and C.C. Conley, "Some Results on the
Stability and Instability of the Backward Differentiation Methods with
Non-Uniform Time Steps," IBM Research Report RC-3964, July 1972,
Proceedings of International Symposium on Numerical Analysis, Dublin, Ireland,
August 1972.
16.
R.K. Brayton, F.G. Gustavson and G.D. Hachtel, "A
New Efficient Algorithm for Solving Differential-Algebraic Systems Using
Implicit Backward Differentiation Formulae," Computer-Aided Circuit
Design, Simulation and Optimization, edited by S. W. Director, Series Benchmark
Papers in Electrical Engineering and Computer Science, Dowden Hutchinson and
Ross, Inc., Stroudsburg, PA, 1973.
17.
R.K. Brayton, "Numerical A-Stability for
Difference-Differential Systems," IBM Research Report, RC-4647, December
1973, Proceedings of the International Symposium on Stiff Differential Systems,
Wildbad, Germany, October 4-6, 1973.
18.
R.K. Brayton, D. Coppersmith and A.J. Hoffman,
"Self-Orthogonal Latin Squares," IBM Research Report, RC-4532,
September 1973.
19.
R.K. Brayton, Alan J. Hoffman and Don Coppersmith,
"Self-orthogonal Latin Squares," Colloquia Internazionalle sulle
TEORIE COMBINATORIE, September 3-15, 1973; Academia Nazionale Dei Lincei, Roma,
pp. 509-517, 1976.
20.
R.K. Brayton, A.J. Hoffman and D. Coppersmith,
"Self-orthogonal Latin Squares of All orders n Except n=2,3,6," IBM
Research Report RC-4532; Bulletin of AMS, Volume 80, No. 1, January 1974.
21.
R.K. Brayton, "Recognition of Hand-Printed
Materials," IBM Technical Memo, April 1976.
22.
R.K. Brayton and C.H. Tong, "Stability of Dynamical
Systems: A Constructive Approach," IBM Research Report RC-7027, February
1978; Proceedings of IEEE International Symposium on Circuits and Systems, May
1978.
23.
G.M. Shepherd and R.K. Brayton, "Analysis of
Dendrodendritic Synaptic Circuit by Computer Simulation," IBM Research
Report RC-7344, October 1978; Brain Research, 175, pp. 377-382, 1979.
24.
R.K. Brayton and C.H. Tong, "Stability of Dynamical
Systems: A Constructive Approach," IEEE Transactions on Circuits and
Systems, CAS-26, pp. 224-234, April 1979.
25.
R.K. Brayton and C.H. Tong , “Constructive Stability and
Asymptotic Stability of Dynamical Systems”, IBM Research Report RC-7909,
October 1979; Proceedings of the International Symposium on Circuits and
Systems, Tokyo, pp. 573-576, 1979; IEEE Transactions on Circuits and Systems,
November 1980.
26.
R.K. Brayton and C. Tong , “Constructive Stability of
Dynamical Systems”, IEEE Conference on Decision and Control Proceedings,
December 1981.
27.
G.M. Shepherd, R.K. Brayton, J.P. Miller, I. Segev, J.
Rinzel and W. Rall , “Signal Enhancement in Distal Dendrites by Means of
Interactions Between Active Dendritic Spines”, Proceedings of the National
Academy of Science, pp. 2192-2195, April 1985.
28.
G.M. Shepherd and R.K. Brayton , “Logic Operations are
Properties of Computer-Simulated Interactions Between Excitable Dendritic
Spines”, IBM Research Report, RC-11804, March 1986.
29.
G.M. Shepherd and R.K. Brayton , “Logic Operations are
Properties of Computer-Simulated Interactions Between Excitable Dendritic
Spines”, Neuroscience 1987 pp 151-165.
30.
R.K. Brayton, "Estimates on Switching Time in a
Circuit Containing One Esaki Diode," RC-338, IBM Research Center, Yorktown
Heights, NY, September 1960.
31.
R.K. Brayton and R. Willoughby, "An Analysis of the
Effect of Component Tolerances on the Amplification of the Balanced-Pair Tunnel
Diode Circuit," RC-673, IBM Research Center, Yorktown Heights, NY, IEEE
Transactions on Electronics and Computers, EC-12, 3, pp. 269-274, June 1963.
32.
R.K. Brayton, W.L. Miranker and R.A. Toupin, "A
Numerical Analysis of a Magneto-Resistive Circuit Employed as a Voltage
Regulator," NC-295, IBM Research Center, Yorktown Heights, NY, September
1963.
33.
R.K. Brayton, "Some Results on the Stability of
Nonlinear Networks Containing Negative Resistances," IEEE Transactions on
Circuit Theory, CT-11, 165-167, March 1964.
34.
R.K. Brayton and J.K. Moser, "A Theory of Nonlinear
Networks, Part I," Applications of Mathematics, XXII, 1 1-33, April 1964.
35.
R.K. Brayton and J.K. Moser, "A Theory of Nonlinear
Networks, Part II," Applications of Mathematics, XXII, 2, 81-104, July
1964.
36.
R.K. Brayton, "Stability Criteria for Large Networks,"
IBM Journal of Research and Development 8, 4, 466-470, September 1964.
37.
R.K. Brayton, "On the Effect of Component Tolerances
in the Balanced- Pair Tunnel-Diode Circuit," IEEE Transactions on Circuit
Theory CT-11, 351-356, September 1964.
38.
R.K. Brayton, "A Canonical Form for Nonlinear RLC
Networks," Proceedings, Symposium on System Theory, Polytechnic Institute
of Brooklyn, NY, April 1965.
39.
R.K. Brayton, "Nonlinear Oscillations in a
Distributed Network," RC-1405, IBM Research Center, Yorktown Heights, NY,
April 1965, Applications of Mathematics XXIV, No. 4, pp. 289-301, January 1967.
40.
R.K. Brayton, "A Small-signal Stability Criterion
for Electrical Networks Containing Lossless Transmission Lines," RC 1686,
IBM Research Center, Yorktown Heights, NY, September 1966, IBM Journal of
Research and Development, pp.431-440, November 1968.
41.
R.K. Brayton, "The Termination Condition for No
Reflection and Infinite Directivity in a Lossles System of Parallel
Conductors," NC-631, IBM Research Center, Yorktown Heights, NY, July 1966.
42.
R.K. Brayton, G.D. Hachtel, F.G. Gustavson and T. Grapes,
"A Sparse Matrix Approach to Network Analysis," RC-2646 IBM Research
Center, Yorktown Heights, NY, August 1969, Proceedings of Second Biannual
Cornell Conference on Computerized Electronics, October 1969.
43.
R.K. Brayton, "Nonlinear Reciprocal Networks,"
RC 2606 September 1969, IBM Research Center, Yorktown Heights, NY, Proceedings
of SIAM-AMS Symposium on Electrical Network Theory, Vol. III, pp. 1-16, 1971.
44.
G.D. Hachtel, R.K. Brayton and F.G. Gustavson, "The
Sparse Tableau Approach to Network Analysis and Design," RC 3008, IBM
Research Center, Yorktown Heights, NY, May 1970 and IEEE Transactions of
Circuit Theory, Vol. CT-18, pp. 111-113, January 1971; The World of Large Scale
Systems, IEEE Press, pp. 4-16, 1982.
45.
R.K. Brayton, Fred G. Gustavson and Gary D. Hachtel,
"A Sparse Tableau Matrix Approach to Network Analysis and Design,"
Chiao Tung Colloquium on Circuits and Systems, Taiwan, Republic of China,
August 1970.
46.
G.D. Hachtel, R.K. Brayton and F.G. Gustavson,
"Large-scale Network Computations Via the Sparse Tableau Approach,"
1970 International Symposium on Circuit Theory, Atlanta, Ha., December 1970,
Digest of Technical Papers, edited by Lewis Winner, New York, pp. 163-164,
1970.
47.
R.K. Brayton, F. G. Gustavson and G. D. Hachtel,
"The Use of Variable-Order Variable-Step Backward Differentiation Methods
for Nonlinear Electrical Networks," Proceedings of IEEE Mexico Conference,
January 1971.
48.
G.D. Hachtel, R.K. Brayton and F.G. Gustavson,
"Sparse Tableau Approach to Nonlinear Adjoint Sensitivity
Computations," Proceedings of IEEE Mexico Conference, January 1971.
49.
G.D. Hachtel, R.K. Brayton and F.G. Gustavson, "The
Sparse Tableau Approach to Network Analysis and Design," Computer-Aided
Circuit Design, Simulation and Optimization, Edited by S.W. Director, Series
Benchmark Papers in Electrical Engineering and Computer Science, Dowden
Hutchinson and Ross, Inc., Stroudsburg, PA, 1973.
50.
R.K. Brayton and S.W. Director, "The Event
Functional and Its Use in Time Domain Optimization," IBM Research Report
RC-5209, February 1975; Proceedings of the International Symposium on Circuits
and Systems, Boston, Mass, April 1975.
51.
R.K. Brayton and S.W. Director, "Computation of
Delay Time Sensitivities for Use in Time Domain Optimization," IEEE
Transactions on Circuits and Systems, Volume CAS-22, No. 12, pp. 910-920,
December 1975.
52.
R.K. Brayton, A.J. Hoffman and T.R. Scott, "A
Theorem on Inverses of Convex Sets of Real Matrices with Application to the
Worst Case DC Problem," Proceedings of the International Symposium on
Circuits and Systems, pp. 82-85, April 1976; IEEE Transactions on Circuits and
Systems, Volume CAS-24, No. 8, pp. 409-415, August 1977.
53.
R.K. Brayton, "Tolerance Assignment and Design
Centering in the Convex Case," IBM Research Report RC-5964, April 1976.
54.
Jane Cullum and R.K. Brayton, "Some Remarks on the
Symmetric Rank One Update," IBM Research Report RC-6157, August 1976;
JOTA, 29, pp. 493-519, December 1979.
55.
R.K. Brayton, "Error Estimates for the Variable-step
Backward Differentiation Methods," IBM Research Report RC-6205, September
1976.
56.
R.K. Brayton and Jane Cullum, "An Algorithm for
Minimizing a Differentiable Function Subject to Box Constraints and
Errors," IBM Research Report RC-6429, March 1977; Proceedings of IEEE
Conference on Decision and Control, December 1976; Proceedings of IEEE
International Symposium on Circuits and Systems, April 1977; JOTA, 29, pp.
521-558, December 1979.
57.
R.K. Brayton and Jane Cullum, "Optimization with the
Parameters Constrained to a Box," Numerical Methods for Differential
Equations and Simulation, North-Holland, 1978.
58.
R.K. Brayton, L.O. Chua, J.D. Rhodes and R. Spence,
"Modern Network Theory-An Introduction," Optimization in Computer
Aided Circuit Design, Georgi Publishing Co. 1978. Book
59.
R.K. Brayton, S.W. Director and G.D. Hachtel,
"Arbitrary Norms for Statistical Design via Linear Programming,"
Proceedings of IEEE International Symposium on Circuits and Systems, May 1978.
60.
R.K. Brayton, S.W. Director, G.D. Hachtel and L.M.
Vidigal, "Yield Maximization and Tolerance Assignment Via Simplicial
Approximation," Proceedings of Electro '78, May 1978.
61.
R.K. Brayton, "Optimization in Computer Aided
Circuit Design," IBM Research Report RC-7159; 1978 European Conference on
Circuit Theory and Design, Volume II-Guest Lectures, pp. 7-63, September 1978.
62.
R.K. Brayton, S.W. Director and G.D. Hachtel, "Yield
Maximization and Worst-Case Design with Arbitrary Statistical
Distributions," IBM Research Report RC-7506, February 1979; IEEE
Transactions on Circuits and Systems, CAS-26, September 1979.
63.
R.K. Brayton, S.W. Director, G.D. Hachtel and L.M.
Vidigal, "A New Algorithm for Statistical Circuit Design Based on
Quasi-Newton Methods and Function Splitting," IBM Research Report RC-7702,
June 1979; Proceedings of IEEE International Symposium on Circuits and Systems,
Tokyo, pp. 280-283, July 1979.
64.
R.K. Brayton, and C.H. Tong , “Some Results on the
Nonlinear Worst-Case Problem”, Proceedings of the IEEE International Symposium
on Circuits and Systems, pp. 1142, April 1980.
65.
R.K. Brayton and R. Spence , “Computer-Aided Circuit
Design: Sensitivity and Optimization”, Elsevier Scientific Publishing Co.,
Amsterdam, 1981. Book
66.
R. Brayton, G. Hachtel and A. Sangiovanni-Vincentelli, A
Survey of Optimization Techniques for Integrated Circuit Design, Proceedings of
IEEE, pp. 1336-1361, October 1981, Invited
Paper.
4.1.1 Two-Level (1982 – 1987)
67.
R.K. Brayton, J. Cohen, G.D. Hachtel, B. Trager and
D.Y.Y. Yun , “Fast Recursive Boolean Function Manipulation”, Proceedings of the
International Symposium on Circuits and Systems, April 1982; IBM Corporate
Symposium on Structured Logic, November 1982.
68.
R.K. Brayton, G.D. Hachtel, L. Hemanchandra, R. Newton
and A. Sangiovanni- Vincentelli , “A Comparison of Logic Minimization
Strategies Using ESPRESSO: An APL Program Package for Partitioned Logic
Minimization”, Proceedings of the International Symposium on Circuits and
Systems, pp. 42-48, Rome, Italy, April 1982.
69.
R. Brayton, G. Hachtel, C. McMullen and A.
Sangiovanni-Vincentelli, ESPRESSO-II: A New Logic Minimizer for Programmable
Logic Arrays Proc. 1984 Custom Integrated Circuits Conference, May 1984.
70.
R. Brayton, G. Hachtel, C. McMullen and A.
Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis
Kluwer Academic Publishers, 1984. Book
71.
R. Brayton, A. Malik, A. R. Newton and A.
Sangiovanni-Vincentelli, A Modified Approach to Two-Level Logic Minimization,
Proc. 1988 Int. Conference. on CAD, pp. 106-109, Santa Clara, CA. November
1988.
72.
R.K. Brayton and F. Somenzi, An Exact Minimizer for
Boolean Relations, IEEE International Conference Computer Aided Design,
November 1989.
73.
R.K. Brayton and F. Somenzi, Minimization of Boolean
Relations, Proc. Int. Symp. Circ. Syst. ISCAS, May 1989.
74.
H. Savoj, A. Malik and R.K. Brayton, Fast Two-Level
Minimizers for Multilevel Logic Synthesis, Proceedings of the IEEE
International Conference on Computer Aided Design, November 1989.
75.
A.A. Malik, R. Brayton, A.R. Newton and A.
Sangiovanni-Vincentelli, Reduced Offsets for Two-Level Multi-Valued Logic
Minimization, Proc. of 1990 27th ACM/IEEE Design Automation Conference, pp.
290-296, June 1990.
76.
A.Malik, R. Brayton, A.R. Newton and A.
Sangiovanni-Vincentelli, Two Level Minimization of Multi-Valued Functions Large
Offset, Research Report No. 16112, IBM, Yorktown, September 1990.
77.
A. Malik, R. Brayton, A.R. Newton and A.
Sangiovanni-Vincentelli, Reduced Offset for Minimization of Binary-valued
Functions, IEEE Trans. on CAD of ICAS, Vol. 10, No. 4, pp. 413-426, April 1991.
78.
Y. Watanabe and R.K. Brayton, Heuristic Minimization of
Boolean Relations, International Workshop on the Logic Synthesis, Research
Triangle Park, May 1991.
79.
R. K. Brayton, P. C. McGeer and J. Sanghavi, "A New
Exact and Heuristic Minimizer for two-Level Logic Synthesis," Proceedings of
the International Symposium of the Kyushu Institute of Technology, July 1992.
80.
P. McGeer, J. Sanghavi, R. K. Brayton and A.
Sangiovanni-Vincentelli, "Minimization of Logic Functions Using Essential
Signature Sets," Proc. 6th International Conference on VLSI India, January
1993, [Best paper].
81.
P. C. McGeer, J. Sanghavi, R. K. Brayton and A.
Sangiovanni-Vincentelli, "An Algorithm for Verifying the Equality of
Signature Cubes," Proceedings of the International Workshop on Logic
Synthesis, May 1993.
82.
G. M. Swamy, R. K. Brayton and P. McGeer, "A Fully
Implicit Quine-McClusky Procedure Using BDD'S," International Workshop on
Logic Synthesis, May 1993 and ERL Memo UCB/ERL M92/127.
83.
P. McGeer, J. Sanghavi, R.K. Brayton and A.
Sangiovanni-Vincentelli , “ESPRESSO-Signature: A New Exact Minimizer for Logic
Functions”, Proceedings of the 30th ACM/IEEE Design Automation Conference, pp.
618-624, Dallas, Texas, June 1993 and IEEE Transactions on Very Large System
Integration (VLSI) Systems, Vol. 1, No. 4, pp. 432-440, December 1993.
84.
R. Murgai, R.K. Brayton and A. Sangiovanni-Vincentelli ,
“Cube-packing and Two-Level Minimization”, Proceedings of the IEEE/ACM
International Conference on CAD, pp. 115-122, Santa Clara, CA November 1993.
85.
T. Villa, A. Saldanha, R. K. Brayton, and A. Sangiovanni-Vincentelli, Symbolic
two-level minimization., IEEE Trans. on CAD, vol.16, (no.7), July 1997.
p.692-708
4.1.2 Multi-level – Technology Independent (1981 – 2001)
86.
R. Brayton, G. Hachtel and A. Sangiovanni-Vincentelli,
Taxonomy of CAD for VLSI, with Proceedings of the 1981 ECCTD, La Hague, Invited
Paper, state-of-the-art review lecture.
87.
R.K. Brayton and C. McMullen , “The Decomposition and
Factorization of Boolean Expressions”, Proceedings of the International
Symposium on Circuits and Systems, April 1982.
88.
R. K. Brayton and C. McMullen , “Automatic Implementation
of Logic”, IBM Corporate Symposium on
Structured Logic, November 1982.
89.
R.K. Brayton and C.T. McMullen, “DESIGN User's Manual for
the Yorktown Logic Editor (YLE)” IBM Technical Memo, 1983.
90.
R.K. Brayton and C.T. McMullen , “Synthesis and
Optimization of Multistage Logic”, ICCD '84, Portchester, NY, October 1984.
91.
R.K. Brayton, N.L. Brenner, C.L. hen, G. DeMicheli, C.T.
McMullen and R.H.J.M. Otten , “The YORKTOWN Silicon Compiler”, International
Symposium on Circuits and Systems 1985, Kyoto, Japan, June 1985.
92.
R.K. Brayton, C.L. Chen, G. DeMicheli, J. Katzenelson,
C.T. McMullen, R.H.J.M. Otten and R.L. Rudell, “A Microprocessor Design Using
the Yorktown Silicon Compiler”, ICCD '85, pp. 225-231, October 1985.
93.
R.K. Brayton, E.Detjens, S. Krishna, T. Ma, P. McGeer, L.
Pei, N. Phillips, R. Rudell, R. Segal, A. Wang, R. Yung and A.
Sangiovanni-Vincentelli , “Multiple-Level Logic Optimization System”, IEEE
1986.
94.
R.K. Brayton , “Algorithms for Optimizing Silicon
Compilers”, Proceedings of Automated Design and Engineering for
Electronics-Japan, Tokyo, Japan, January 1986.
95.
R.K. Brayton , “Factoring Logic Functions”, IBM Journal
of Research and Development, May 1986.
96.
R.K. Brayton, “Algorithms for Multi-Level Logic Synthesis
and Optimization”, IBM Research Report RC-11938, July 1986. L'Aquila, Italy,
July 1986; Design Systems for VLSI Circuits: Logic Synthesis and Silicon
Compilation, (ed. P. Antognetti, G. de Micheli, A. Sangiovanni-Vincentelli, M. Nijhoff),
pp.197-249, 1987.
97.
R. Brayton, E. Detjens, S. Krishna, T. Ma, P. McGeer, L.
Pei, N. Phillips, R. Rudell, A. Sangiovanni-Vincentelli, R. Segal, A. Wang, R.
Yung, Multiple-Level Logic Optimization System, International Conference on
Computer-aided Design, Santa Clara, October 1986.
98.
R. Brayton, G. Hachtel, C. McMullen, R. Rudell and A.
Sangiovanni-Vincentelli, Multi-level Logic Optimization Algorithms for VLSI
Synthesis, Kluwer Academic Publisher, 1986.
99.
R.K. Brayton, R. Rudell, A. Sangiovanni-Vincentelli and
A. Wang , “Multi-Level Logic Optimization and The Rectangle Covering Problem”,
Proceedings of the 1987 IEEE International Conference on Computer-Aided Design,
Santa Clara, November 1987.
100. R. Brayton, R. Rudell, A.
Sangiovanni-Vincentelli and A. Wang, MIS: A Multiple-Level Logic Optimization
System, IEEE Trans. on CAD/ICAS, Vol. CAD-6, No. 6, pp.1062-1082, November
1987.
101. R.K. Brayton R.
Camposano, G. DeMicheli, R.H.J.M. Otten and J. van Eindhoven , “The Yorktown
Silicon Compiler”, IBM Research Report RC-12500; Silicon Compilation edited by
D.D. Gajski, Addison-Wesley, 1988.
102. R.K. Brayton and A.
Sangiovanni-Vincentelli, Logic Research at Berkeley, SRC TECHCON, Dallas Texas,
July 1988.
103. P. McGeer and R.K.
Brayton, Efficient Prime Factorization of Logic Expressions, Design Automation
Conference, June 1989.
104. A. Malik, R.K. Brayton
and A. Sangiovanni-Vincentelli, Logic Minimization for Factored Forms, Proc.
1989 Int. Conference. on Comp. Design, Boston, pp. 396-399, October 1989.
105. R. Brayton, G. Hachtel
and A. Sangiovanni-Vincentelli, Multilevel Logic Synthesis, Proceedings of the
IEEE, Vol. 78, No. 2, pp. 264-300, February 1990 Invited Paper.
106. R. Murgai, R.K. Brayton
and A. Sangiovanni-Vincentelli, “Optimum Functional Decomposition Using
Encoding”, Proceedings of the 31st ACM/IEEE Design Automation Conference, pp.
408-414, San Diego, CA June 1994.
107. Szu-Tsung Cheng, Robert
K. Brayton, "Synthesizing Multi-Phase HDL Programs", Proceedings of
International Verilog Conference, 1996.
108. S. P. Khatri, R. K. Brayton,
and A. L. Sangiovanni-Vincentelli, A VLSI
Design Methodology using a Network of PLAs embedded in a Regular Layout Fabric
IEEE/ACM International Conference on CAD, ICCAD 00,
109. Yunjian Jiang; Brayton, R.K. Logic optimization and
code generation for embedded control applications Ninth International
Symposium on Hardware/Software Codesign. CODES 2001
110. R. Brayton, “The Future of Logic Synthesis and
Verification”, Logic Synthesis and
Verification, S. Hassoun, T. Sasao (editors) R. Brayton (consulting
editor), Kluwer Academic Press, 2001 book
chapter
4.1.3 Incremental Re-Synthesis –
Engineering Change (1991 – 1997)
111. Y. Watanabe and R. K.
Brayton, Incremental Synthesis for Engineering Changes, International Workshop
on the Logic Synthesis, Research Triangle Park, May 1991, International
Conference on Computer Design, Boston, October 1991.
112. Y. Watanabe and R. K.
Brayton, Incremental Synthesis for Engineering Changes, IEICE Transactions Vol.
J74-A, No.2, pp162-169, February 1991.
113. Y. Kukimoto, M. Fujita
and R.K. Brayton , “A Redesign Technique for Combinational Circuits Based on
Gate Reconnections”, Proceedings of the IEEE/ACM Conference on CAD, pp.
632-637, San Jose, CA November 1994.
114. G. M. Swamy, S. Rajamani,
C. Lennard and R. K. Brayton, "Minimal Logic Re-Synthesis", Technical
Report UCB/ERL M96/22, Electronics Res. Lab., University of California,
Berkeley, CA 94720
115. G. Swamy,
4.1.4 BDDs, SAT, Covering Problems etc.
(1989 – 2002)
116. S. Malik, R. Brayton and
A. Sangiovanni-Vincentelli, Encoding Symbolic Inputs for Multi-level Logic
Implementation, Proc. VLSI 89 IFIP Conference, Munich, pp. 221-230, August
1989.
117. A. Saldanha, T. Villa, R.
K. Brayton and A. Sangiovanni-Vincentelli, A Framework for Satisfying Input and
Output Encoding Constraints, Proc. 28th ACM/IEEE DAC Conference, San Francisco,
pp. 170-175, June 1991.
118. P. McGeer, H. Savoj, R.
K. Brayton and A. Sangiovanni-Vincentelli, "Minimizing Logic Functions
Through Binary Decision Diagrams," DAC'92, June 1992.
119. W. Lam and R. K. Brayton,
"On Relationship Between ITE and BDD," International Conference on
Computer Design '92, Boston, Massachusetts, October 1992.
120. W. Lam and R. K. Brayton,
"Some Properties of If-Then-Else DAG's," DAC'92, June 1992.
121. A. Aziz, S. Tasiran and
R. K. Brayton, “BDD Variable Ordering for Interacting Finite State Machines”,
Intl. Workshop on Logic Synthesis, Tahoe City, CA May 1993, Memorandum No.
UCB/ERL M93/71 October 1993 and Proceedings of the 31st IEEE/ACM Design
Automation Conference, pp. 283-288, San Diego, CA June 1994.
122. E. Felt, G. York, R.K.
Brayton and A. Sangiovanni-Vincentelli , “Dynamic Variable Reordering for BDD
Minimization”, Proceedings of the European Design Automation Conference with
EURO-VHDL'93, pp.130-135, CCH Hamburg, Germany September 1993.
123. T. Shiple, R.K. Brayton
and A. Sangiovanni-Vincentelli , “Computing Boolean Expressions with
OBDDs”, Memorandum No. UCB/ERL M93/84
December 1993.
124. T. Shiple, R. Hojati,
R.K. Brayton and A. Sangiovanni-Vincentelli , “Heuristic Minimization of BDDs
Using Don't Cares”, Memorandum No. UCB/ERL M93/58, July 1993 and Proceedings of
the 31st IEEE/ACM Design Automation Conference, pp. 225-231, San Diego, CA June
1994.
125. A. Narayaan, S. Khatri,
J. Jain, M. Fujita, R. Brayton, and A. Sangiovanni-Vincentelli,
"Compositional Techniques for Mixed Bottom-Up/Top-Down construction of
ROBDDs", Tech. Report UCB/ERL M95.51, June 1995.
126. A. Narayaan, S. Khatri,
J. Jain, M. Fujita, R. Brayton, and A. Sangiovanni-Vincentelli, "A Study
of Compositional Schemes for Mixed Apply/Compose Based Constructions of ROBDDs",
Int. Conf on VLSI Design, India, Jan. 1995.
127. M. Fujita and Y. Kukimoto
and R. K. Brayton, "BDD Minimization by Truth Table Permutations",
Proceedings of International Conference on Circuits and Systems, 596-599, IV,
May, 1996
128. J. Jain, Narayan, Coelho,
Khatri, Sangiovanni-Vincentelli, Brayton, Fujita. "Decomposition Techniques
for Efficient ROBDD Construction" Presented at the International
Conference on Formal Methods in Computer-Aided Design, Palo Alto, CA, Nov 1996.
129. Jagesh V. Sanghavi and
Rajeev K. Ranjan and Robert. K. Brayton and Alberto Sangiovanni-Vincentelli,
"High Performance BDD Package Based on Exploiting Memory Hierarchy",
DAC, June, 1996
130. Rajeev K. Ranjan and
Jagesh V. Sanghavi and Robert. K. Brayton and Alberto Sangiovanni-Vincentelli,
"Using Network of Workstations for Efficient Binary Decision Diagram
Manipulation", ICCD, Austin, Texas, USA, October, 1996
131. R. Ranjan, W. Gosti, R.
Brayton, A. Sangiovanni-Vincentelli, "Dynamic Reordering in a
Breadth-First Manipulation Based BDD Package: Challenges and Solutions",
International Workshop on Logic Synthesis (IWLS), May 1997.
132. A. Narayan, A. Isles, J.
Jain, R. Brayton, A. Sangiovanni-Vincentelli, Reachability Analysis Using
Partitioned-ROBDDs, IEEE/ACM International
Conference on CAD, ICCAD 97, pp. 388-393, November 1997.
133. E. I. Goldberg, Y. Kukimoto, R. K. Brayton, Preventing
OBDD Blow-ups via Domain Transformations Guided by High-Level Specifications,
International Workshop on Logic Synthesis (IWLS), Tahoe City, CA Workshop Notes
Volume 2, 317-333, February 1998.
134. E. Goldberg, T. Villa, R. Brayton, A.
Sangiovanni-Vincentelli, A Fast and Robust Exact Algorithm for Face
Embedding, IEEE/ACM International Conference on CAD, ICCAD 97, pp. 296-303,
November 1997.
135. E. Goldberg, L. Carloni, T.
Villa, R. Brayton, A. Sangiovanni-Vincentelli, Negative Thinking by
Incremental Problem Solving: Application to Unate Covering, IEEE/ACM
International Conference on CAD, ICCAD 97, pp. 91-97, November 1997.
136. T. Kam, T. Villa, R. K.
Brayton, and A. Sangiovanni-Vincentelli, Explicit and implicit algorithms
for binate covering problems, IEEE Trans. on CAD, vol.16, (no.7), July
1997. p.677-91
137. E. Goldberg, T. Villa, R.
Brayton, A. Sangiovanni-Vinceltenni, "Theory and Algorithms for Face
Hypercube Embedding", International Workshop on Logic Synthesis (IWLS),
May 1997.
138. E. Goldberg, L. Carloni,
T. Villa, R. Brayton, A. Sangiovanni-Vincentelli, "Negative Thinking in
Search Methods; Application to Unate Covering, International Workshop on Logic
Synthesis (IWLS), May 1997.
139. T. Kam, T. Villa, R.
Brayton, A. Sangiovanni-Vincentelli, Multi-valued decision diagrams: theory
and applications, International Journal on Multiple-Valued Logic Volume 4,
Numbers 1-2 (1998), pages 9-62.
140. E. Goldberg, T. Villa, R. Brayton, A. Sangiovanni-Vincentelli,
Theory and Algorithms for Face Hypercube Embedding, IEEE Trans. on CAD,
June 1998, vol.17, (no.6): 472-88.
141. L.P. Carloni, E. I.
Goldberg, T. Villa, R. K. Brayton, A. Sangiovanni-Vincentelli, Aura II:
Combining Negative Thinking and Branch-and-Bound in Unate Covering Problems,
VLSI: Integrated Systems on Silicon: (P. Ivey and J. Marques-Silva editors),
Kluwer 1999.
142. Carloni, L.P.; Goldberg, E.I.; Villa, T.; Brayton, R.K. AURA
II: combining negative thinking and branch-and-bound in unate covering problems
VLSI: Systems on a Chip. IFIP TC10 WG10.5 Tenth International Conference on
Very Large Scale Integration (VLSI'99)
143. E. I. Goldberg, L. P. Carloni,
T. Villa, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, Negative
Thinking in Branch-and-Bound: The Case of Unate Covering, IEEE Trans. on
CAD, March 2000, vol. 19, (no. 3): 281-294.
144. Evgueni Goldberg, Mukul R Prasad, Robert K Brayton Using
Problem Symmetry in Search Based Satisfiability Algorithms in Proceedings
of the Design Automation & Test in Europe Conference (DATE 2002), pp.
134-141, March 2002, Paris, France. best
paper
4.1.5 Technology Mapping and FPGA Synthesis
(1980 – 2000)
145. R.K. Brayton and R.H.
Risch ,”Combinational Logic Design Using Cascode Current Switch”, ICCC Proceedings, Rye, NY, October 1980.
146. R.K. Brayton, C.L. Chen,
R.H.J.M. Otten and Y.Y. Yamour , “An SCVS/Domino Silicon Compiler for Automated
Macro Design”, IBM Technical Memo, 1984.
147. R.K. Brayton, C.L. Chen,
C.T. McMullen, R.H.J.M. Otten and Y.Y. Yamour , “Automatic Implementation of
Switching Functions as Dynamic CMOS Circuits”, CICC, May 1984; Digital VLSI
Systems, Ed. M.I. Elmasry, IEEE Press, pp. 225-229, 1985.
148. C. Moon, B. Lin and R.K.
Brayton, “Technology Mapping for Sequential Logic Synthesis”, International
Workshop on Logic Synthesis, May 1989.
149. R. Murgai, Y. Nishizaki,
N. Shenoy, R. Brayton and A. Sangiovanni-Vincentelli, Logic Synthesis for
Programmable Gate Arrays, Proc. of 1990 27th ACM/IEEE Design Automation
Conference, pp. 620-625, June 1990.
150. A. Malik, D. Harrison, and
R. Brayton, “Three-Level Decomposition with Application to PLDs”, Proc. of IEEE
International Conference on Computer Design, October 1991.
151. R. Murgai, R. K. Brayton,
N. Shenoy and A. Sangiovanni-Vincentelli, Improved Logic Synthesis Algorithms
for Table Look-Up Architectures, Proc. of ICCAD-91, pp. 564-567, November 1991.
152. R. Murgai, R. K. Brayton
and A. Sangiovanni-Vincentelli, "On the Complexity of Boolean Functions
for Table Look Up Architectures," 2nd International Workshop on Field
Programmable Logic and Applications, Vienna, Austria, September 1992.
153. R. Murgai, R. K. Brayton
and A. Sangiovanni-Vincentelli, "An Improved Synthesis Algorithm for
Multiplexor-based PGA's," Proceedings of the 29th Design Automation
Conference pp. 380-387, 1992.
154. H. Savoj, M. J. Silva, R.
K. Brayton and A. Sangiovanni-Vincentelli, "Boolean Matching in Logic
Synthesis," Proceedings of the European Design Automation Conference -
EURO DAC - EURO VHDL, pp. 168- 177.
155. P. R. Stephan and R. K.
Brayton, "A Synthesis and Verification Criterion for Logic Gate
Models," IWLS, May 1993.
156. P. R. Stephan and R. K.
Brayton, "Physically Realizable Gate Models," UC Berkeley ERL Memo
UCB/ERL M93/33, May 1993.
157. R. Murgai, R.K. Brayton and
A. Sangiovanni-Vincentelli , “Some Results on the Complexity of Boolean
Functions for Table Look Up Architectures”, Proceedings of the International
Conference on Computer Design, October 1993 and submitted to the Journal of
VLSI Design 1993.
158. R. Murgai, R.K. Brayton
and A. Sangiovanni-Vincentelli, “Logic Synthesis for Field-Programmable Gate
Arrays”, Kluwer Academic Publishers, July 1995. Book
159. M. Prasad, D.
Kirkpatrick, R. Brayton, A. Sangiovanni-Vincentelli, "Domino Logic
Synthesis and Technology Mapping", International Workshop on Logic
Synthesis (IWLS), May 1997.
160. D. Jongeneel, R. Otten, Y.
Watanabe, R. K. Brayton, Area and Search Space Control for Technology
Mapping, Proceedings 2000 Design Automation Conference, 37th
DAC, 86-91, Los Angeles, CA June 2000
4.1.6 Delay Optimization (1988 – 1994)
161. R. Brayton, A.
Sangiovanni-Vincentelli, K. Singh and A. Wang, Timing Optimization of
Combinational Logic, Proc. 1988 Int. Conference. on CAD, pp. 282-285, November
1988.
162. H.J. Touati, Ch.W. Moon
and R. K. Brayton , “Performance-Oriented Technology Mapping” Proceedings of
MIT VLSI Conference, 1990.
163. A. Saldanha, R.K. Brayton
and A. Sangiovanni-Vincentelli, Redundancy and Delay in Logic Optimization, In
the Extended Abstract Vol. of TECHCON'90, San Jose, CA., October 1990.
164. S. Malik, K. J. Singh, R.
K. Brayton and A. Sangiovanni-Vincentelli, Performance Optimization of
Pipelined Circuits, Proc. of ICCAD-90, pp. 410-413, November 1990.
165. A. Saldanha, R. K.
Brayton and A. Sangiovanni-Vincentelli, Timing Optimization with Testability
Considerations, Proc. of ICCAD-90, pp. 460-463, November 1990.
166. H. Touati, H. Savoj and
R.K. Brayton, Delay Optimization of Combinational Logic Circuits through
Clustering and Partial Collapsing, 1991 International Workshop on Logic
Synthesis April 1991.
167. R. Murgai, R. K. Brayton
and A. Sangiovanni-Vincentelli, On Clustering for Minimum Delay/Area, Proc. of
ICCAD-91, pp. 6-9, November 1991.
168. N. Shenoy, R. K. Brayton,
R. Murgai and A. Sangiovanni-Vincentelli, Performance Directed Synthesis for
Table Look-Up Programmable Gate Arrays, Proc. of ICCAD-91, pp. 572-575,
November 1991.
169. P.McGeer, R.K. Brayton,
A. Sangiovanni-Vincentelli and S. Sahni, Performance Enhancement Through the
Generalized Bypass Transform, International Workshop on Logic Synthesis, 1991
and International Conference on Computer-Aided Design, 1991.
170. A. Saldanha and R. K.
Brayton," Optimizing Logic for Speed Size and Testability," Keynote
Address at CompEuro'92 IEEE International Conference on Computer Systems and
Software Engineering, The Hague, May 4, 1992. Chapter in book Computer Systems
and Software Engineering Kluwer Academic Press, May 1992, eds. P. Dewilde and
J. Vandewalle.
171. A. Saldanha, R.K. Brayton
and A. Sangiovanni-Vincentelli , “Circuit Structure Relations to Redundancy and
Delay”, IEEE Transactions on Computer-Aided Design, to appear 1994.
4.1.7 Flexibilities – Don’t Cares and SPFDs
(1986 – 2002)
172. K. Bartlett, R.K.
Brayton, C. Hachtel, R. Jacoby, R. Rudell, A. Sangiovanni-Vincentelli and A.
Wang , “Multi-Level Logic Minimization Using Implicit Don't Cares”, ICCD '86,
Rye, NY; pp. 552-557, October 1986.
173. K. Bartlett, R. Brayton,
G. Hachtel, R. Jacobi, R. Rudell, A. Sangiovanni-Vincentelli and A. Wang,
Multi-level Logic Minimization Using Implicit Don't-Cares, IEEE Trans. on CAD
of ICAS, June 1988.
174. P. McGeer and R.K.
Brayton, Consistency and Observability Invariance in Multi-Level Logic
Synthesis, IEEE International Conference on Computer-Aided Design, May 1989.
175. R.K. Brayton, E.M.
Sentovich and F. Somenzi, Don't Cares and the Global Flow Analysis of Boolean
Networks, Proceedings of ICCAD, November 1988.
176. P.C. McGeer and R.K.
Brayton, The Observability Don't-Care Set and Its Approximations, and at the
International Conference on Computer Design in October 1990.
177. R. K. Brayton and F.
Somenzi, Boolean Relations and Incomplete Specification of Logic Networks,
International Conference VLSI, August 1989.
178. R. Brayton, A.
Sangiovanni-Vincentelli, A. Saldanha and A. Wang, Multi-level Logic
Simplification Using Don't-Cares and Filters, Proc. of 1989 Design Automation
Conference, pp. 277-282, June 1989.
179. H. Savoj and R. K.
Brayton, The Use of Image Computation Techniques in Extracting Local Don't
Cares and Network Optimization, ICCAD November 1991.
180. H. Savoj and R.K.
Brayton, Observability Relations and Observability Don't Cares, ICCAD, November
1991.
181. Y. Watanabe, L. Guerra
and R. K. Brayton, "Logic Optimization with Multi-Output Gates,"
ICCD'93.
182. E. M. Sentovich, V.
Singhal and R. K. Brayton, "Multiple Boolean Relations,"
International Workshop on Logic Synthesis, Tahoe City, CA, May 1993.
183. R.K. Brayton and E.M.
Sentovich , Network Hierarchies and Node Minimization, IEICE Transactions on
Information and Systems, Vol. E78-D, No. 3, Tokyo, Japan, March 1995 and in the
Formal Methods in System Design 6, pp. 191-216 Kluwer Academic Publishers,
Boston - Manufactured in The Netherlands 1995.
184. R. Brayton,
"Understanding SPFDs: A New Method for Specifying Flexibility"
International Workshop on Logic Synthesis (IWLS), May 1997.
185. S. Sinha, R. K. Brayton, Implementation and Use of
SPFDs in Optimizing Boolean Networks, International Workshop on Logic
Synthesis (IWLS), Tahoe City, CA Workshop Notes Volume 2, 499-507, June 1998.
186. Subarnarekha Sinha, Robert K. Brayton Implementation and use of
SPFDs in optimizing Boolean networks, Proceedings of the 1998 International
Conference on CAD, ICCAD 98, November 1998.
187. S. P. Khatri, S. Sinha, A.
Kuehlmann, R. K. Brayton, A. Sangiovanni-Vincentelli, SPFD-based Wire Removal
in a Network of PLAs, International Workshop on Logic Synthesis (IWLS), Granlibakken, CA, Workshop Handouts 271-280, June 1999.
188. Brayton, R.K. Compatible observability don't cares
revisited IEEE/ACM International Conference on Computer Aided Design. ICCAD
2001
189. S. Sinha R. K. Brayton Improved
Robust SPFD Computations IEEE IWLS 2001, International Workshop on Logic
Synthesis 2001, Workshop Notes
190. Subarnarekha Sinha, Alan Mishchenko and
R. K. Brayton Topologically Constrained Logic Synthesis IEEE/ACM International
Conference on CAD, ICCAD 2002,
191. Subarna Sinha, Alan Mishchenko, R.
K. Brayton Topologically Constrained Logic Synthesis, IEEE IWLS 2002,
International Workshop on Logic Synthesis 2002, Workshop Notes
4.1.8 Asynchronous (1990 – 1994)
192. P. McGeer and R.K.
Brayton, Hazard Prevention in Combinational Circuits, Hawaii International
Conference on the System Sciences, 1990, [Best paper].
193. Ch. Moon, P. Stephan and
R.K. Brayton, Synthesis of Hazard-Free Asynchronous Circuits from Graphical
Specifications, ICCAD, November 1991.
194. C. Moon, P. Stephan and
R. K. Brayton, "Synthesis and Verification of Asynchronous Circuits from
Graphical Specification," Journal of VLSI Signal Processing, Kluwer
Academic Publishers, 1992.
195. C.W. Moon and R.K.
Brayton, " Elimination of Dynamic Hazards By Factoring," Proceedings
of the 30th Design Automation Conference, pp.7-18, Dallas, Texas June 1993.
196. Ch. Moon, P. Stephan and
R.K. Brayton, Specification, Synthesis and Verification of Hazard-free
Asynchronous Circuits, Proc. International Workshop on Logic Synthesis, May
1991 and Journal of VLSI Signal Processing, pp. 299-314, November 1993 and in
the Journal of VLSI Processing, 7, pp. 85-100, Kluwer Academic Publishers,
Boston. Manufactured in the Netherlands 1994.
4.1.9 Multi-Valued Logic (1990 – 2002)
197. L. Lavagno, S. Malik, R.
K. Brayton and A. Sangiovanni-Vincentelli, MIS-MV: Optimization of Multi-Level
Logic with Multiple-valued Inputs, Proc. of ICCAD-90, pp. 560-563, November
1990.
198. S. Malik, A. Srinivasan,
T. Kam and R. Brayton, Algorithms for Discrete Function Manipulation,
Proceedings of the International Conference on Computer-Aided Design, November
1990.
199. T. Kam and R. Brayton,
Multi-valued Decision Diagram, Master Thesis, UC Berkeley, 1990. Also, UC
Berkeley Electronics Research Laboratory, Memorandum No. UCB/ERL M90/125, 1990.
200. Y. Watanabe and R.K.
Brayton, Heuristic Minimization of Multiple-Valued Relations, International
Conference on Computer-Aided Design, Santa Clara, November 1991.
201. A. Malik, R.K. Brayton,
A.R. Newton and A. Sangiovanni-Vincentelli , “Two-Level Minimization of
Multivalued Functions with Large Offsets”, IEEE Transactions on Computer,
Vol.42, No.11, pp. 1325-1342, November 1993.
202. Y. Watanabe, R. K.
Brayton and A. Sangiovanni-Vincentelli, "Heuristic Minimization of
Multiple-Valued Relations," IEEE Transaction of Computer-Aided Design,
June 1993.
203. T. Kam, T. Villa, R.
Brayton, A. Sangiovanni-Vincentelli, Multi-valued decision diagrams: theory
and applications, International Journal on Multiple-Valued Logic Volume 4,
Numbers 1-2 (1998), pages 9-62.
204. S. P. Khatri, R. K. Brayton,
and A. L. Sangiovanni-Vincentelli, Multi-valued Network Simplification using
Redundancy Removal Presented at SRC Techcon,
205. R. K. Brayton, and S. P. Khatri,
Multi-valued Logic Synthesis International Conference on VLSI Design,
206. S. P. Khatri, R. K. Brayton,
and A. L. Sangiovanni-Vincentelli, Sequential Multi-valued Network
Simplification using Redundancy Removal International Conference on VLSI
Design,
207. Y. Jiang, and R. K. Brayton, Don't Cares and
Multi-Valued Logic Network Minimization IEEE/ACM International Conference
on CAD, ICCAD 00,
208. S. Sinha, S. P. Khatri, R. K. Brayton, and A. L. Sangiovanni-Vincentelli, Binary
and Multi-Valued SPFD-based Wire Removal in PLA Networks IEEE/ACM
International Conference on Computer Design, ICCD 00, Austin, TX, 2000.
209. N. Yevtushenko, T. Villa, R. K. Brayton, A. Petrenko,
A. L. Sangiovanni-Vincentelli, Synthesis by Language Equation Solving:
Extended Abstract, IEEE IWLS 2000, International Workshop on Logic
Synthesis 2000,
210. Y. Jiang, R. K. Brayton, Don't Cares and
Multi-Valued Logic Minimization, IEEE IWLS 2000, International Workshop on
Logic Synthesis 2000,
211. M. Gao, R. K. Brayton, Semi-Algebraic Methods for
Multi-Valued Logic, IEEE IWLS 2000, International Workshop on Logic
Synthesis 2000, Dana Point, CA, Workshop Notes 73-80, May 31 - June 2, 2000.
212. Y. Jiang, Minxi Gao, Subarna
Sinha, and Robert K. Brayton An Optimizing
Software Compiler Based on Multi-Valued Logic Optimization TechCON, Semiconductor Research Corporation,
213. Minxi Gao and Robert Brayton Multi-Valued
Multi-Level Network Decomposition IEEE IWLS 2001, International Workshop on
Logic Synthesis 2001, Workshop Notes
214. Jie-Hong Jiang, Yunjian Jiang, Robert K. Brayton An
implicit method for multi-valued network encoding IEEE IWLS 2001,
International Workshop on Logic Synthesis 2001, Workshop Notes
215. Elena Dubrova, Yunjian Jiang, Robert Brayton Minimization of
Multiple-Valued Functions in Post Algebra IEEE IWLS 2001, International Workshop on Logic
Synthesis 2001, Workshop Notes
216. M. Gao, J.-H. Jiang, Y. Jiang, Y. Li,
217. A Mishchenko, Robert. K. Brayton A Theory of
Non-Deterministic Networks International Symposium on Boolean Problems,
218. Yunjian Jiang; Robert K. Brayton Software Synthesis
from Synchronous Specifications Using Logic Simulation Techniques Proceedings
of the 39th Design Automation Conference (DAC-02), New Orleans, LA,
June 2002.
219. Alan Mishchenko, R. K. Brayton A Boolean Paradigm
in Multi-Valued Logic Synthesis, IEEE IWLS 2002, International Workshop on
Logic Synthesis 2002, Workshop Notes
220. Alan Mishchenko, R. K. Brayton Simplification of
Non-Deterministic Multi-Valued Networks , IEEE IWLS 2002, International
Workshop on Logic Synthesis 2002, Workshop Notes
221. Jie-Hong Jiang, Alan Mishchenko, R. K. Brayton Reducing
Multi-Valued Algebraic Operations to Binary, IEEE IWLS 2002, International
Workshop on Logic Synthesis June 2002, Workshop Notes.
222. M. Gao, J-H. Jiang, Y. Jiang, Y. Li, A. Mishchenko, S.
Sinha, T. Villa, and R. Brayton Optimization of Multi-Valued Multi-Level
Networks, International Symposium on Multiple-Valued Logic May 2002 invited
talk
223. A. Mishchenko and R. Brayton, A Theory of Non-Deterministic Networks, Workshop on Boolean
Problems, Sept. 2002 invited paper.
4.2.1 State
Assignment, State Minimization, and Encoding (1984 – 1997)
224. G. DeMicheli, R. Brayton
and A. Sangiovanni-Vincentelli, KISS: A Program for Optimal State-Assignment of
Finite State Machines Proceedings of the 1984 International Conference on CAD,
November 1984.
225. Optimal State Assignment
for Finite State Machines, (G. DeMicheli, R.K. Brayton and A.
Sangiovanni-Vincentelli), IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems, July 1985.
226. L. Lavagno, S. Malik, R.
K. Brayton. and A. Sangiovanni-Vincentelli, " Symbolic Minimization of
Multilevel Logic and the Input Encoding Problem," IEEE Trans. on CAD of ICAS,
Vol.11, No.7, pp. 825-843, July 1992.
227. L. Lavagno, C-W. Moon, R.
K. Brayton and A. Sangiovanni-Vincentelli, "Solving the State Assignment
Problem for Signal Transition Graph," Proc. 29th ACM/IEEE DAC Conference,
Anaheim, pp.568-572, June 1992.
228. L. Lavagno, C.W. Moon, R.
K. Brayton and A. Sangiovanni-Vincentelli, "A Novel Framework for Solving
the State Assignment Problem for Event-based Specifications," Technical
Report UCB/ERL M92/19, March 1992.
229. T. Kam, T. Villa, R. K.
Brayton and A. Sangiovanni-Vincentelli,"Implicit Generation of Compatible
for Exact State Minimization," Memorandum No. UCB/ERL M93/60 August 1993.
230. A. Saldanha, T. Villa,
R.K. Brayton and A. Sangiovanni-Vincentelli , “Satisfaction of Input and Output
Encoding Constraints”, IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems, Vol. 13, No. 5, pp. 589-602, May 1994.
231. A. Aziz, V. Singhal, G.M.
Swamy and R.K. Brayton , “Minimizing Interacting Finite State Machines: A
Compositional Approach to Language Containment”, Memorandum No. UCB/ERL M93/68,
September 1993 and Proceedings of International Conference on Computer Design,
Cambridge, MA October 1994.
232. T. Kam, T. Villa, R.K.
Brayton and A. Sangiovanni-Vincentelli , “A Fully Implicit Algorithm for Exact
State Minimization”, Memorandum No. UCB/ERL M93/79 November 1993 and in the
Proceedings of the 31st ACM/IEEE Design Automation Conference, pp. 684-690, San
Diego, CA June 1994.
233. L. Lavagno, C.W. Moon,
R.K. Brayton and A. Sangiovanni-Vincentelli , “An Efficient Heuristic Procedure
for Solving the State Assignment Problem for Event-Based Specifications”, IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.
14, No. 1, pp. 45-60, January 1995.
234. T. Kam, T. Villa, R. K.
Brayton, and A. Sangiovanni-Vincentelli, Theory and algorithms for state
minimization of nondeterministic FSMs, IEEE Trans. on CAD, vol.16, (no.11)
Nov. 1997, p.1311-22.
235. T. Kam, T. Villa, R. K.
Brayton, and A. Sangiovanni-Vincentelli, Implicit computation of compatible
sets for state minimization of ISFSMs, IEEE
Trans. on CAD, vol.16, (no.7), July 1997. p.657-76
4.2.2 Retiming (1990
– 2001)
236. S. Malik, E. Sentovich,
R. Brayton and A. Sangiovanni-Vincentelli, Retiming and Resynthesis: Optimizing Sequential
Networks with Combinational Techniques, Proc. 23rd Annual Hawaii International
Conference on Systems Sciences, Minitrack on Synthesis, pp. 397-406, January
1990.
237. E. Sentovich and R. K.
Brayton, Retiming Don't Cares, IWLS, May.
238. E.M. Sentovich and R.K.
Brayton. Preserving don't care conditions during retiming. In VLSI 91. IFIP
TC10/WG 10.5 International Conference Edinburgh,, pages 461-70, 20-22 Aug.
1991.
239. N. Shenoy and R. Brayton,
Retiming of Circuits with single-Phase Transparent Latches, ICCD October 1991.
240. S. Malik, E. Sentovich
and R. Brayton and A. Sangiovanni-Vincentelli, Retiming and Resynthesis:
Optimizing Sequential Networks with Combinational Techniques, IEEE Trans. on
CAD of ICAS, Vol. 10, No. 1, pp. 74-84, January 1991.
241. S. Malik, K.J. Singh, R.
K. Brayton and A. Sangiovanni-Vincentelli, "Performance Optimization of
Pipelined Logic Circuits Using Peripheral Retiming and Resynthesis," IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.
12, No. 5 pp.568-578, May 1993.
242. V. Singhal, C. Pixley and
R.K. Brayton, Power-up Delay for Retiming Digital Circuits, , Proceedings of
International Symposium on Circuits and Systems, Seattle, Washington, May 1995.
243. V. Singhal, C. Pixley,
R.L. Rudell and R.K. Brayton, The Validity of Retiming Sequential Circuits, ,
Proceedings of the 32nd Design Automation Conference, pp. 316-321, San
Francisco, CA June 1995.
244. Vigyan Singhal, Sharad
Malik, Robert K. Brayton. "The Case for Retiming with Explicit Reset
Circuitry". In Proc. of Intl. Conf. on Computer-Aided Design, San Jose,
CA, November 1996.
245. R. K. Ranjan, V. Singhal, R. Somenzi, R. K. Brayton, On the optimization
power of retiming and resynthesis transformations, Proceedings of the 1998
International Conference on CAD, ICCAD 98, November 1998.
246. P. Chong, R. Brayton Characterization
of Feasible Retimings , IEEE IWLS 2001, International Workshop on Logic
Synthesis 2001, Workshop Notes
4.2.3 Sequential
Flexibility (1993 – 2003)
247. H.Y. Wang and R.K.
Brayton , “Input Don't Care Sequences in FSM Networks”, Proceedings of the
IEEE/ACM International Conference on CAD, pp. 321-328, Santa Clara, CA November
1993.
248. H-Y. Wang and R. K.
Brayton, "Computation of Sequential Input Don't Care Sequences in FSM
Networks of Arbitrary Topologies," International Workshop on Logic
Synthesis, May 1993.
249. Y. Watanabe and R. K
Brayton, "The Maximum Set of Permissible Behaviors for FSM Networks,"
Proceedings of the International Conference on CAD, pp. 316-320, Santa Clara,
CA November 1993.
250. H.Y. Wang and R.K.
Brayton , “Permissible Observability Relations in FSM Networks”, Memorandum No.
UCB/ERL M94/15, February 1994 and Proceedings of the 31st Design Automation
Conference, pp. 677-684, San Diego, CA June 1994.
251. C. Pixley, V. Singhal, A.
Aziz and R.K. Brayton , “Multi-Level Synthesis for Safe Replaceability”,
Memorandum No. UCB/ERL M94/31, April 1994 and Proceedings of International
Conference on Computer-Aided Design, San Jose, CA 1994.
252. A. Aziz, F. Balarin, R.K.
Brayton and A. Sangiovanni-Vincentelli , “Sequential Synthesis Using SIS”, To
be published in ICCAD'95 in November 1995.
253. Wang, H.-Y. and Brayton,
R. K. Logic Optimization of FSM Networks Using Input Don't Care Sequences
UCB/ERL M95/42 University of California, Berkeley, June 1995
254. Wang, H.-Y. and Brayton,
R. K. Multi-level Logic Optimization of FSM Networks IEEE International
Conference on Computer-Aided Design 728-735 November 1995 San Jose, CA
255. Shaz Qadeer, Robert K.
Brayton, Vigyan Singhal, Carl Pixley. "Latch Redundancy Removal without
Global Reset". In Proceedings of International Conference on Computer
Design, Austin, TX, October 1996.
256. Takeshi Kitahara and
Robert K. Brayton "Low Power synthesis via Transparent Latches and
Observability Don't Cares", ERL Memo. No. UCB/ERL M96/64 25 October, 1996
257. R. Brayton, A. Mehrotra,
S. Qadeer, V. Singhal, "Sequential Optimization Without State Space
Exploration", International Workshop on Logic Synthesis (IWLS), May 1997.
258. A. Mehrotra, S. Qadeer, V. Singhal, R. K.
Brayton, A. Aziz, A. L. Sangiovanni-Vincentelli, Sequential Optimization
Without State Space Exploration, IEEE/ACM International Conference on CAD,
ICCAD 97, pp. 208-215, November 1997.
259. T. Kitahara, R. Brayton, Low
power synthesis via transparent latches and observability don't cares,
Proceedings of 1997 IEEE International Symposium on Circuits and Systems. ISCAS
'97,
260. A. Aziz, F. Balarin, R. K. Brayton, and A.
Sangiovanni-Vincentelli, Sequential Synthesis Using S1S, IEEE Trans. on
CAD, October 2000, vol. 19, (no. 10): 1149-1162.
261. Nina Yevtushenko, Tiziano
Villa, Robert Brayton, Alex Petrenko, Alberto Sangiovanni-Vincentelli Solution
of Parallel Language Equations for Logic Synthesis IEEE IWLS 2001,
International Workshop on Logic Synthesis 2001, Workshop Notes
262. Yevtushenko, N.; Villa, T.; Brayton, R.K.; Petrenko,
A. Solution of parallel language equations for logic synthesis. IEEE/ACM
International Conference on Computer Aided Design. ICCAD 2001
263. S. Sinha A. Kuehlmann R. K.
Brayton Sequential SPFDs IEEE IWLS 2001, International Workshop on Logic
Synthesis 2001, Workshop Notes
264. Sinha, S.; Kuehlmann, A.; Brayton, R.K. Sequential SPFDs
IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001
265. Singhal, V.; Pixley, C.; Aziz, A.;
Brayton, R.K. Theory of safe replacements for sequential circuits IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems,
vol.20, (no.2), IEEE, Feb. 2001. p.249-65
266. Nina Yevtushenko, T. Villa, R. Brayton, A. Petrenko,
and A. Sangiovanni-Vincentelli Equisolvability
of Series vs. Controller's Topology in Synchronous Language Equations, IEEE
IWLS 2002, International Workshop on Logic Synthesis 2002, Workshop Notes
267. N. Yevtushenko, T. Villa, R. Brayton, A. Petrenko, and
A. Sangiovanni-Vincentelli Sequential Synthesis by Language Solving IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems, To
appear
268. Yunjian Jiang, R. K. Brayton Don't Care Computation
in Minimizing Extended Finite-State Machines with Presburger Arithmetic,
IEEE IWLS 2002, International Workshop on Logic Synthesis 2002, Workshop Notes
269. V. Singhal and C. Pixley and A. Aziz and S. Qadeer and R.
Brayton, Sequential Optimization in the
Absence of Global Reset, ACM Transactions on Design Automation of
Electronic Systems (TODAES), vol. 8,
no.2, April 2003.
4.2.4 General (1990 –
2002)
270. H. J. Touati, H. Savoj,
B. Lin, R. K. Brayton and A. Sangiovanni-Vincentelli, Implicit State
Enumeration of Finite State Machines using BDD's, Proc. of ICCAD-90, pp.
130-133, November 1990.
271. R. Murgai, R. K. Brayton
and A. Sangiovanni-Vincentelli, "Sequential Synthesis for Table Look up
PGAs," Euro-Asic, Paris, May 1992.
272. E. M. Sentovich, J. K.
Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj, P. R. Stephan, R.
K. Brayton and A. Sangiovanni-Vincentelli, "SIS: A System for Sequential
Circuit Synthesis," Technical Report UCB/ERL M92/41, May 1992.
273. E. M. Sentovich K. J.
Singh, C. Moon, H. Savoj, R. K. Brayton and A. Sangiovanni-Vincentelli,
"Sequential Circuit Design Using Synthesis and Optimization,"
Proceedings of the International Conference on Computer Design, October 1992.
274. R. Murgai, R. K. Brayton
and A. Sangiovanni-Vincentelli, "Sequential Synthesis for Table Look Up
Programmable Gate Arrays," Proceedings of the 30th Design Automation
Conference, pp.224-229, Dallas, Texas June 1993 and submitted to the Journal of
VLSI Design 1993.
275. N.V. Shenoy, R.K. Brayton
and A. Sangiovanni-Vincentelli, "Resynthesis of Multi-Phase
Pipelines," Proceedings of the 30th Design Automation Conference, pp.
490-496, Dallas Texas June 1993.
276. V. Singhal, Y. Watanabe
and R. K. Brayton, "Heuristic Minimization of Synchronous Relations,"
International Workshop on Logic Synthesis, Tahoe City, CA May 1993 also in
International Conference on Computer Design, Boston, MA, October 1993.
277. Y. Matsunaga, P. C.
McGeer, and R. K. Brayton, "On Computing the Transitive Closure of a State
Transition Relation," design Automation Conference, June 1993, and
Proceedings of the International Workshop on Logic Synthesis, May 1993.
278. A. Aziz and R.K. Brayton
, “Synthesizing Interacting Finite State Machines”, Memorandum No. UCB/ERL
M94/96, December 1994.
279. V. Singhal, C. Pixley, A.
Aziz and R.K. Brayton , “Exploiting Power-up Delay for Sequential Optimization”,
Proceedings of European Design Automation Conference, Brighton, Great Britain,
September 1995.
280. S.-T. Cheng, R. K. Brayton, G. York, K. A. Yelick, and A. Saldanha,
Compiling Verilog into Timed
281. T. Kam, T. Villa, R.
Brayton and A. Sangiovanni-Vincentelli, "Synthesis of Finite State
Machines: Functional Optimization", Kluwer Academic Publishers, November
1996. Book
282. Thomas R. Shiple, Vigyan
Singhal, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli. "Analysis
of Combinational Cycles in Sequential Circuits". In Proc. of Intl.
Symposium on Circuits and Systems, Atlanta, GA, May 1996.
283. L. Carloni, T. Villa, T.
Kam, R. Brayton and A. Sangiovanni-Vincentelli, "Generation of a Minimal
STG from an Implicit Cover", UC Berkeley Electronics Research Laboratory,
Technical Report No. UCB/ERL M96/40, June 1996.
284. S. Krishnan, S. Khatri,
A. Narayan, K. McMillan, R. K. Brayton, and A. Sangiovanni-Vincentelli
"Engineering Change in a non-deterministic FSM setting", IEEE/ACM
Design Automation Conference 1996, Las Vegas, NV, pp. 451-456.
285. T. Kam, T. Villa, R.
Brayton and A. Sangiovanni-Vincentelli, "Synthesis of Finite State
Machines: Logic Optimization", Kluwer Academic Publishers, May 1997. Book
286. Szu-Tsung Cheng, Alexander Saldanha,
Patrick C. McGeer, Patrick Scaglia,
Robert K. Brayton , “The
Synchronous Semantics of Verilog: A Functional Interpretation of Verilog
Programs”, Cadence Technical Conference, 1997
287. Szu-Tsung Cheng, PatrickC. McGeer, Tom Truman, Patrick Scaglia,
Alberto Sangiovanni-Vincentelli, Robert K. Brayton, “
288. M. Baleani, F. Gennari, Y. Jiang, Y. Patel, R. K. Brayton, A.
Sangiovanni-Vincentelli HW/SW Partitioning and Code Generation of Embedded
Control Applications on a Reconfigurable Architecture Platform Tenth
International Symposium on Hardware/Software Codesign.
CODES 2002
289. R.K. Brayton, Chen, Jess,
Otten and van Ginneken, Wire Planning for Stackable Designs, Symposium on VLSI
Technology, Systems and Applications, Taipei, Taiwan, May 1987.
290. M. Beardslee, Ch. Kring,
R. Murgai, H. Savoj, R. K. Brayton and A.R. Newton, “SLIP: A Software
Environment for System Level Interactive Partitioning”, IEEE International
Conference Computer Aided Design, November 1989.
291. R. H. J. M. Otten, R. Brayton, Planning for
Performance, Proceedings of the 35th Design Automation
Conference (DAC 98), pp.122-127,
292. W. Gosti, A. Narayan, R. K. Brayton, A. L. Sangiovanni-Vincentelli, Wireplanning
in Logic Synthesis, International Workshop on Logic Synthesis (IWLS), Tahoe
City, CA Workshop Notes Volume 2, 520-529, June 1998.
293. W. Gosti, A. Narayan, R. Brayton, A. Sangiovanni-Vincentelli, Wireplanning
in Logic Synthesis, Proceedings of the 1998 International Conference on
CAD, ICCAD 98, November 1998.
294. S. Khatri, A. Mehrotra, R. Brayton, A. Sangiovanni-Vincentelli, R. H. J.
M. Otten, A novel VLSI Layout Fabric for Deep Sub-Micron Applications,
Proceedings of the 36th Design Automation Conference (DAC-99), pp.
491-496, New Orleans, LA, June 1999.
295. A. Tabbara, R. K. Brayton,
and A. R. Newton, Retiming for DSM with area-delay trade-offs and delay
constraints, Proceedings of the 36th Design Automation
Conference (DAC-99),
296. P. Chong and R. Brayton Estimating
and optimizing routing utilization in DSM design SLIP'99: Workshop on
System-Level Interconnect Prediction, Apr. 1999
297. Otten, R.H.J.M.; Brayton, R.K. Performance planning
Integration, The VLSI Journal, vol.29, (no.1), Elsevier, March 2000.
p.1-24.
298. P. Chong, Y. Jiang, S. Khatri, F. Mo, S. Sinha, R. Brayton, Don't Care Wires in
Logical/Physical Design, IEEE IWLS 2000, International Workshop on Logic
Synthesis 2000, Dana Point, CA, Workshop Notes 1-9, May 31 - June 2, 2000.
299. Tabbara, A.; Tabbara, B.; Brayton,
R.K.;
300. F. Mo, A. Tabbara, and R. K.
Brayton, A Force-Directed Macro-Cell Placer IEEE/ACM International
Conference on CAD, ICCAD 00,
301.
302. Mo, F.; Tabbara, A.;
Brayton, R.K. A force-directed maze router IEEE/ACM International
Conference on Computer Aided Design. ICCAD 2001
303. S. P. Khatri, R. K. Brayton,
and A. Sangiovanni-Vincentelli, “Cross-Talk Immune VLSI Design Using Regular
Layout Fabrics”, Kluwer Academic Press,
2001 Book
304.
305.
306. Fan Mo and R. Brayton, PLA-Based Regular Structures
and Their Synthesis, IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems, To appear
307. R. McGeer, R. Brayton, R.
Rudell and A. Sangiovanni-Vincentelli, Extended Stuck-Fault Testability for
Combinational Circuits, in Advanced Research in VLSI W. Dally, ed., pp.
239-259, The MIT Press, 1990.
308. P. R. Stephan, R. K.
Brayton and A. Sangiovanni-Vincentelli, "Combinational Test Generation
Using Satisfiability," UC Berkeley ERL Memo UCB/ERL M92/112 October 1992
and submitted to IEEE Trans. CAD, November 1992.
309. P. Stephan and R. K.
Brayton, "TEGUS:Test Generation Using Satisfiability," ITC'92, June
1992.
310. A. Saldanha, R. K.
Brayton and A. Sangiovanni-Vincentelli, "Equivalence of Robust Delay-Fault
and Single Stuck-Fault Test Generation," Proceedings of the ACM
International Workshop on Timing Issues in the Specification and Synthesis of
Digital System, March 1992 and Proceedings of the Design Automation Conference,
pp. 173-176, Anaheim CA, June 1992.
311. W. Lam, A. Saldanha, R.
K. Brayton and A. Sangiovanni-Vincentelli, "Delay fault testing: Trading
Fault Coverage, Test Set Size, and Performance," (Emphasis on Theory)
Research on Integrated Systems:Proceedings of the Symposium on Integrated
Systems, Seattle - WA, pp. 68-87, March 1993, Gaetano Borriello and Carl
Ebeling editors, The MIT Press, March 1993
312. W. Lam, R. K. Brayton and
A. Sangiovanni-Vincentelli, "Delay Fault Coverage, Test Set Size, and
Performance Tradeoffs," Proceedings of the 30th ACM/IEEE Design Automation
Conference, pp.446-452, Dallas, Texas June 1993.
313. C. Wawrukiewicz, A.
Saldanha, R.K. Brayton and A. Sangiovanni-Vincentelli , “Sequential Test
Pattern Generation: Using Implicit STG Traversal Techniques to Generate Test
and Identify Redundancies in Sequential Circuits”, Memorandum No. UCB/ERL
M94/4, February 1994.
314. W.K. Lam, A. Saldanha,
R.K. Brayton and A. Sangiovanni-Vincentelli , “Delay Fault Coverage, Test Set
Size and Performance Trade-Offs”, IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems, Vol. 14, No. 1, pp. 32-44, January 1995.
315. P. Stephan, Robert K.
Brayton and Alberto L. Sangiovanni-Vincentelli, "Combinational Test
Generation Using Satisfiability", IEEE Transactions on Computer-Aided
Design of Intergrated Circuits and Systems, Vol. 15, No. 9, pp. 1167-1175,
September 1996.
316. Z.C. Li, R. Brayton,
"Efficient Identification of Non-Robustly Untestable Path Delay
Faults" ITC, Nov. 1997.
317. R. Brayton, S. Malik, A.
Sangiovanni-Vincentelli and A. Wang, Logic Verification Using Binary Decision
Diagrams in a Logic Synthesis Environment, Proc. 1988 Int. Conference. on CAD,
pp. 6-9, November 1988.
318. N. Shenoy, K.J. Singh, R.
K. Brayton and A. Sangiovanni-Vincentelli, "On the Temporal Equivalence of
Sequential Circuits," Proc. 29th ACM/IEEE DAC Conference, Anaheim,
pp.405-409, June 1992.
319. E. I. Goldberg, Y. Kukimoto, R. K. Brayton, Combinational
verification based on high-level functional specifications. Proceedings of
Design, Automation and Test in
320. Evguenii I Goldberg, Mukul R Prasad and Robert K Brayton SAT
Procedures for Combinational Equivalence Checking in Proceedings of the
Cadence Technical Conference, April 2000. Also, in Proceedings of the Third
Workshop on the Satisfiability Problem (SAT 2000), May 2000
321. R. K. Ranjan, V. Singhal, F. Somenzi, and R. K. Brayton, R.K. Using
combinational verification for sequential circuits, Proceedings of Design,
Automation and Test in Europe Conference and Exhibition, Munich, Germany, 9-12
March 1999.
322. E. I. Goldberg, M. R. Prasad, R. K. Brayton, Using
SAT for Combinational Equivalence Checking, IEEE IWLS 2000, International
Workshop on Logic Synthesis 2000, Dana Point, CA, Workshop Notes 185-191, May
31 - June 2, 2000.
323. Goldberg, E.I.; Prasad, M.R.; Brayton, R.K. Using
SAT for combinational equivalence checking Proceedings Design, Automation
and Test in
324. S. Quer, G. Cabodi, P. Camurati, L. Lavagno,
E. M. Sentovich, and R. K. Brayton, Verification
of similar FSMs by mixing incremental re-encoding, reachability analysis, and
combinational checks, Formal Methods in System Design, vol.17, (no.2),
Kluwer Academic Publishers, Oct. 2000. p.107-34.
325. Jie-Hong Jiang, R. K. Brayton On the Verification of
Sequential Equivalence, IEEE IWLS 2002, International Workshop on Logic
Synthesis 2002, Workshop Notes
326. J.-H. Roland Jiang and R. Brayton On the
Verification of Sequential Equivalence IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems, To appear
327. H. Touati, R.K. Brayton
and R. Kurshan , “Testing Language Containment for w-Automata using BDD's”,
1991 International Workshop on Formal Methods in VLSI Design January 1991 Miami
and in the Information and Computation Journal, Vol. 118, No.1 printed in
Belgium 1995.
328. M. Chiodo, T. R. Shiple,
A. Sangiovanni-Vincentelli and R. K. Brayton, "Automatic Reduction in CTL
Compositional Model Checking," UCB Memo UCB/ERL M92/55, January 1992,
Proc. Fourth Workshop on Computer-Aided Verification, Montreal, pp.225-238,
June 1992, also appeared in Lecture Notes in Computer Science, Vol. 663,
editors of LNCS 663, G. Von Bochmann and D.K. Probst.
329. R. Hojati, H. Touati,
R.P. Kurshan and R.K. Brayton , “Efficient Omega-Language Containment”,
Proceedings of the 4th International Conference on Computer-Aided Verification
Workshop, Montreal, Canada, June 1992.
330. M. Chiodo , T. R. Shiple,
A. Sangiovanni-Vincentelli and R. K. Brayton, "Automatic Compositional
Minimization in CTL Model Checking," ICCAD pp.172-178, November 1992.
331. A. Aziz and R.K. Brayton
, “Verifying Interacting Finite State Machines”, Memorandum No. UCB/ERL ???/??,
July 1993.
332. R. Hojati, R.K. Brayton
and R.P. Kurshan , “BDD-Based Debugging of Designs Using Language Containment
and Fair CTL”, Proceedings of of the 5th International Conference on
Computer-Aided Verification Conference, Elounda, Crete, Greece, June 1993.
333. R. Hojati, T. R. Shiple,
R. K. Brayton and R. P. Kurshan, "A Unified Approach to Language
Containment and Fair CTL Model Checking," DAC'93 Dallas, Texas, June 1993.
334. R. Hojati and R. K.
Brayton, "An Environment for Formal Verification Based on Symbolic
Computations," submitted to Formal Methods in System Design Journal 1993.
335. W. Lam and R. K. Brayton,
"Alternating RQ Timed Automata", International Conference on Computer
Aided Verification, 1993 Elounda, Greece, Lecture Notes in Computer Science,
Costa Courcoubetis editor, Springer-Verlag, June 1993.
336. R.. K. Brayton, “Logic
Synthesis and Design Verification”, Costas Courcoubetis (Ed.): Computer Aided
Verification, 5th International Conference, CAV '93,
337. R. Hojati, T.R. Shiple,
R.K. Brayton and R.P. Kurshan, “A Unified Approach to Language Containment and
Fair CTL Model Checking”, Proceedings of the 30th IEEE/ACM Design Automation
Conference, pp. 475-481, Dallas, June 1993.
338. R. Hojati, R.
Mueller-Thuns and R.K. Brayton , “Improving Language Containment Using Fairness
Graphs”, Proceedings of the 6th International Conference on Computer-Aided
Verification, Stanford, California 1994.
339. R. Hojati, V. Singhal and
R.K. Brayton , “Edge-Streett-Edge-Rabin Automata Environment for Formal
Verification Using Language Containment”, Memorandum No. UCB/ERL M94/12, March
1994.
340. R. Hojati, S. Krishnan
and R.K. Brayton , “Heuristic Algorithms for Early Quantification and Partial
Product Minimization”, Memorandum No. M94/11, March 1994.
341. A. Aziz, F. Balarin, S.T.
Cheng, R. Hojati, S.C. Krishnan, R.K. Ranjan, T.R. Shiple, V. Singhal, S.
Tasiran, H.Y. Wang, R.K. Brayton and A. Sangiovanni- Vincentelli , “HSIS: A
BDD-Based Environment for Formal Verification”, Proceedings of the 31st
ACM/IEEE Design Automation Conference, pp. 454-459, San Diego, CA June 1994.
342. A. Aziz, T.R. Shiple, V.
Singhal, R.K. Brayton and A. Sangiovanni- Vincentelli , “Formula-Dependent
Equivalence for Compositional CTL Model Checking”, Memorandum No. UCB/ERL
M94/78, June 1994.
343. A. Aziz, V. Singhal, F.
Balarin, R.K. Brayton and A. Sangiovanni-Vincentelli , “Equivalences for Fair
Kripke Structures”, Proceedings of the ICALP, Jerusalem, July 1994.
344. N. Ishiura and R.K.
Brayton , “A Comparative Approach to Processor Verification Using Symbolic
Model Checking”, Memorandum No. UCB/ERL M94/59, August 1994.
345. G.M. Swamy and R.K.
Brayton , “Incremental Formal Design Verification”, Memorandum No. UCB/ERL
M94/76, August 1994 and Proceedings of the IEEE/ACM Conference on CAD, pp.
458-465, San Jose, CA November 1994.
346. R.K. Ranjan, A.Aziz, R.K.
Brayton, B. Plessier and C. Pixley , “Efficient Formal Design Verification:
Data Structure + Algorithms”, Memorandum No. UCB/ERL M94/100, October 1994.
347. R.K. Ranjan and R.K.
Brayton , “A User Friendly Environment for Property Specification”, Memorandum
No. UCB/ERL M94/99, October 1994.
348. S. C. Krishnan, A. Puri, and
R. K. Brayton. Deterministic !-automata vis-a-vis Deterministic Buchi Automata. In Algorithms and Computation, volume 834 of LNCS,
pages 378-386. Springer-Verlag, 1994.
349. F. Balarin, R. K. Brayton, S.-T. Cheng, D. A.
Kirkpatrick, A. Sangiovanni-Vincentelli, “A Medthodology for Formal Verification of
Real-Time Systems”, ERL Memo M95/11 1995
350. S. C. Krishnan, A. Puri, and
R. K. Brayton. Structural Complexity of !-automata. In
Symposium on Theoretical Aspects of Computer Science, volume 900 of LNCS, pages
143-156. Springer-Verlag, 1995.
351. S. C. Krishnan, A. Puri, R.
K. Brayton and P.Varaiya: The Rabin Index and Chain Automata, with
Applications to Automatas and Games. CAV 1995 pp.
253-266
352. R. Hojati and R.K.
Brayton , “Automatic Datapath Abstraction In Hardware Systems”, Conference on
Hardware Description Language, Tokyo, Japan August 1995.
353. R. Hojati and R.K.
Brayton, An Environment for Formal Verification Based on Symbolic Computations,
, Formal Methods in System Design, 6, pp. 191-216, Kluwer Academic Publishers,
Boston. Manufactured in the Netherlands, March 1995. 1995.
354. R. Hojati and R.K.
Brayton , “Automatic Datapath Abstraction of Hardware Systems”, Computer-Aided
Verification, Belgium, July 1995.
355. A. Aziz, F. Balarin, M.D.
Di Benedetto, R.K. Brayton, A. Saldanha and A. Sangiovanni-Vincentelli ,
“Supervisory Control of Finite State Machines”, Proceedings of Computer Aided
Verification: 7th International Conference, LNCS Vol. 939, Leige, Belgium, July
1995.
356. A. Aziz, V. Singhal, F.
Balarin, R.K. Brayton and A. Sangiovanni-Vincentelli, “It Usually Works: The
Temporal Logic of Stochastic Systems”, Proceedings of Computer Aided
Verification: 7th International Conference, LNCS Vol. 939, Leige, Belgium, July
1995.
357. R. Hojati, R.
Mueller-Thuns, P. Lowenstein and R.K. Brayton , “Automatic Verification of
Memory Systems which Execute Instructions Out of Order”, Conference on Hardware
Descriptions Languages and Their Applications, Tokyo, Japan, September 1995.
358. S. Tasiran, R. Hojati and
R.K. Brayton , “Language Containment of Non-Deterministic W-Automata,” Hardware
Design and Verification Conference, Frankfurt, Germany, October 1995.
359. G.M. Swamy, R.K. Brayton
and V. Singhal , “Incremental Methods for FSM Traversal”, Proceedings of International Conference on
Computer Design, Austin, Texas, October 1995.
360. S. Tasiran and R.
Brayton, "On Iterative Verification with Timed Automata" Digest of
Papars, TAU'95, Nov. 1995.
361. Robert K. Brayton and
Gary D. Hachtel, Alberto Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz,
Szu-Tsung Cheng, Stephen Edwards, Sunil Khatri, Yuji Kukimoto, Abelardo Pardo,
Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali
Swamy, Tiziano Villa, "VIS: A System for Verification and Synthesis",
UC Berkeley Electronics Research Laboratory, Technical Report No. UCB/ERL
M95/104, December 1995.
362. Adnan Aziz, Kumud Sanwal,
Vigyan Singhal, and Robert K. Brayton. "Verifying Continuous Time Markov
Chains", In Proc. of Conference on Computer-Aided Verification, Rutgers,
NJ, July 1996.
363. R. Hojati, A. Isles, D.
Kirkpatrick, R. K. Brayton, "Verification Using Uninterpreted Functions
and Finite Instantiations", Formal Methods in Computer-Aided Design
(FMCAD), November 1996.
364. R. Hojati, S. Krishnan,
R. K. Brayton, "Early Quantification and Partitioned Transition
Relations", International Conference on Computer Design (ICCD), October
1996.
365. A. Isles, R. Hojati, R.
K. Brayton, "Reachability Analysis of ICS Models", SRC Techcon,
September 1996.
366. S. Tasiran, R. Alur, R.
P. Kurshan and R. K. Brayton, "Verifying Abstractions of Timed
Systems", In Proc. Seventh International Conference on Concurrency Theory,
CONCUR '96, LNCS 1119, Springer-Verlag, pages 546-562, August 1996.
367. Robert K. Brayton and
Gary D. Hachtel, Alberto Sangiovanni-Vincentelli, Fabio Somenzi, Adnan Aziz,
Szu-Tsung Cheng, Stephen Edwards, Sunil Khatri, Yuji Kukimoto, Abelardo Pardo,
Shaz Qadeer, Rajeev K. Ranjan, Shaker Sarwary, Thomas R. Shiple, Gitanjali
Swamy, Tiziano Villa, "VIS: A System for Verification and Synthesis",
lncs, 1102, 1996, July, Proceedings of the Conference on Computer-Aided
Verification, Eds. RajeeeAlur and Thomas A. Henzinger, 428-432, Springer, New
Brunswick, NJ
368. R. K. Brayton and G. D.
Hachtel and A. Sangiovanni-Vincentelli and F. Somenzi and A. Aziz and S.-T.
Cheng and S. A. Edwards and S. P. Khatri and Y. Kukimoto and A. Pardo and S.
Qadeer and R. K. Ranjan and S. Sarwary and T. R. Shiple and G. Swamy and T.
Villa, "VIS", Proceedings of the First International Conference on
Formal Methods in Computer-Aided Design, 248-256, November, 1996
369. S. Quer, G. Cabodi, P.
Camurati, L. Lavagno, E. Sentovich, Robert K. Brayton, "Incremental
Re-encoding for Symbolic Traversal of Product Machines", EuroDAC96,
Geneva, September 1996
370. R. Hojati, A. Keuhlmann,
S. German, R. Brayton, "Validity Checking in the Theory of Equality with
Uninterpreted Functions Using Finite Instantiations" International
Workshop on Logic Synthesis (IWLS), May 1997.
371. G. Swamy, S. Edwards, R.
Brayton, "Efficient Verification Using Design Commonalities"
International Workshop on Logic Synthesis (IWLS), May 1997.
372. S. Tasiran, R. Brayton,
"STARI: A Case Study in Compositional and Hierarchical Timing
Verification", CAV, June 1997.
373. S. Qadeer, S. Rajamani,
R. Brayton, T. Henzinger, "Partial Order Reduction in Symbolic State Space
Exploration" CAV, June, 1997.
374. R. Hojati, D. L. Dill, R. K.
Brayton. Verifying linear temporal properties of data insensitive
controllers using finite instantiations. International Conference on
Computer Hardware Description Languages and their Applications, (Hardware
Description Languages and their Applications. Specification, Modelling, Verification and Synthesis of Microelectronic
Systems. IFIP TC10 WG10.5
375. S. Tasiran, S. P. Khatri, Yovine, R. K. Brayton,
and A. L. Sangiovanni-Vincentelli, A Timed Automaton-based Method for Accurate
Circuit Delay Computation in the Presence of Cross-talk International
Conference on Formal Methods in Computer-Aided Design, Palo Alto, CA, Nov 1998
376. A. J. Isles, R. Hojati, and
R. K. Brayton, Computing reachable control states of systems modeled with uninterpreted functions and infinite memory,
Proceedings of CAV'98, 10th International Conference on Computer Aided
Verification,
377. Gurmeet Singh Manku, Ramin Hojati, and Robert K.
Brayton Structural Symmetry and Model Checking, Proceedings of CAV'98,
10th International Conference on Computer Aided Verification, Vancouver, BC,
Canada, June 1998.
378. A. Kuehlmann, K. McMillan, R. Brayton, Probabilistic
State Space Search, IEEE/ACM International Conference on CAD, ICCAD 99, pp.
574-579, November 1999.
379. A. Aziz, K. Sanwal, V. Singhal, and R. Brayton, Model-Checking Continuous Time
Markov Chains, ACM Transactions on Computational Logic 1 (2000), no. 1,
162--170.
380. Alur, R.; Brayton, R.K.; Henzinger, T.A.; Qadeer, S.; Rajamani, S.K. Partial-order
reduction in symbolic state-space exploration Formal Methods in System
Design, vol.18, (no.2), Kluwer Academic Publishers, March 2001. p.97-116
381. A. Aziz, T. Shiple, V. Singhal, R. Brayton, and A. Sangiovanni-Vincentelli Formula
Dependent Equivalence for Compositional CTL Model Checking Journal of
Formal Methods in System Design, pp 193-224, Sept. 2002
382. A. Aziz, F. Balarin, V. Singhal,
R. Brayton, and A. Sangiovanni-Vincentelli Equivalances
for Fair Kripke Structures Chicago Journal of Theoretical Computer Science,
To appear
383. R.L. Bauer, J. Fang, A.
P-C Ng and R.K. Brayton, XPSim: A MOS VLSI Simulator, IEEE International
Conference on Computer-Aided Design, 198?, ICCAD, pp.10, Santa Clara, November
1987.
384. Romy L. Bauer, J. Fang,
A. P-C Ng, and R.K. Brayton, XPSim: a MOS VLSI Simulator, IEEE International
Conference on Computer-Aided Design, 1988.
385. P. McGeer and R.K.
Brayton, Provably Correct Critical Paths, Decennial CalTech VLSI Conference,
May 1989.
386. P. McGeer and R.K.
Brayton, Efficient Algorithms for Computing the Longest Viable Path in a
Combinational Network, Circuits and Systems, Design Automation Conference, June
1989.
387. P.C. McGeer and R.K.
Brayton, Timing Analysis on Precharged-Unate Networks, Design Automation
Conference, June 1990.
388. P.C. McGeer and R.K.
Brayton, A Timing Analysis and Robust Path Delay-Fault Testability through
Linear Path Recursive Functions, International Workshop on Logic Synthesis, May
1991, and International Conference on Computer-Aided Design, 1991.
389. A. Saldanha, R. K.
Brayton, P. C. McGeer, P. Stephan and A. Sangiovanni-Vincentelli , “Timing
Analysis and Delay-Fault Test Generation Using Path Recursive Functions”, Proc.
of ICCAD-91, pp. 180-183, November 1991.
390. P. C. McGeer, R. K.
Brayton, and A. L. Sangiovanni-Vincentelli, “The False Path Problem and its
Implications”, Kluwer Academic Publishers, 1991 Book.
391. P. C. McGeer, A.
Saldanha, P. Stephan, R. K. Brayton and A. Sangiovanni-Vincentelli, "Delay
Models and Sensitization Criteria in the False Path Problem," Proceedings
of the International Symposium on Logic Synthesis and Microprocessor
Architecture, Iizuka - Japan, pp. 76-83, July 1992.
392. A. Saldanha, R. K.
Brayton and A. Sangiovanni-Vincentelli, "Circuit Structure Relations to
Redundancy and Delay: The KMS Algorithm Revisited," Proceedings of the ACM
International Workshop on Timing Issues in th Specification and Synthesis of
Digital Systems (TAU-92) Princeton, March 1992 and Proceedings of the Design
Automation Conference, pp. 245-248, June 1992.
393. P. McGeer, A. Saldanha,
R. K. Brayton and A. Sangiovanni-Vincentelli, " Delay Models and Exact
Timing Analysis," Chapter of book New Trends in Logic Synthesis and
Optimization, Kluwer Academic Publishers, September 1992, ed. T. Sasao.
394. P. Gutwin, P.C. McGeer
and R. K. Brayton, "Delay Models for Technology-Independent Logic
Equations," Proceedings International Conference on Computer Design,
October 1992.
395. R. K. Brayton, P. McGeer,
J. V. Sanghavi and A. Sangiovanni-Vincentelli, "A New Exact Minimizer for
Two-Level Logic Synthesis," Book Chapter in Logic Synthesis and
Optimization edited by T. Sasao - Kluwer Academic Publishers, pp. 1-31, 1992.
396. P. Gutwin, P. C. McGeer
and R. K. Brayton, "A New Technology-Independent Delay Model based upon
the Shannon Cofactor," TAU'92.
397. P. Gutwin, R. McGeer and
R. K. Brayton, "Delay Prediction for Technology-Independent Logic
Equations," DAC'92, June 1992.
398. A. Saldanha, R. K.
Brayton and A. Sangiovanni-Vincentelli, "Circuit Structure Relations to Redundancy
and Delay: The KMS Algorithm Revisited," Proceedings of The Design
Automation Conference, pp. 245-248, Anaheim CA, June 1992.
399. W. Lam and R. K. Brayton,
"Verification with Timed Automata," UC Berkeley ERL Memo UCB/ERL
M92/58, May 1992.
400. W. Lam, R. K. Brayton and
A. Sangiovanni-Vincentelli, "Exact Delay Computation with Timed Boolean
Function," UC Berkeley ERL Memo UCB/ERL M92/57, May 1992.
401. W. Lam, R. K. Brayton and
A. Sangiovanni-Vincentelli, "Minimum Cycle Time of Synchronous Circuit
with Bounded Delays," UC Berkeley ERL Memo UCB/ERL M92/56, May 1992.
402. W. Lam, R. K. Brayton and
A. Sangiovanni-Vincentelli, "Valid Clocking in Wavepipelined
Circuits,"IEEE/ACM International Conference on Computer Aided Design, 1992
Santa Clara, CA. November 1992.
403. W. Lam, R. K. Brayton,
and A. Sangiovanni-Vincentelli, "A Real-Time Decision diagram for Timing
and Power Analysis" (submitted to ICCAD), Nov. 1994.
404. W. Lam, R.K. Brayton and
A. Sangiovanni-Vincentelli , “Exact Minimum Cycle Times for Finite State
Machines”, Memorandum No. UCB/ERL M93/40 May 1993, 1993 ACM Workshop on Timing
Issues in the Specification and Synthesis of Digital Systems, Malente, Germany,
September 1993 and Proceedings of the 31st IEEE/ACM Design Automation
Conference, pp. 100-105, San Diego, CA June 1994.
405. W. Lam, R. K. Brayton and
A. Sangiovanni-Vincentelli, "Exact Minimum Delay Computation and Clock
Frequencies," UC Berkeley ERL Memo UCB/ERL M93/40, June 1993.
406. W. Lam, R. K. Brayton and
A. Sangiovanni-Vincentelli, "Circuit Delay Models and Their Exact
Computation Using Timed Boolean Functions," Proceedings of the 30th Design
Automation Conference, pp. 123-128, Dallas Texas June 1993.
407. W. Lam, R.K. Brayton and
A. Sangiovanni-Vincentelli, “Circuit Delay Models and Their Exact Computation
Using Timed Boolean Functions”, Proceeding of the 30th ACM/IEEE Design
Automation Conference, pp. 128-134, Dallas, Texas June 1993.
408. W. Lam, R.K. Brayton and
A. Sangiovanni-Vincentelli , “Serial and Interleaving Pipelining for General
Sequential Machines”, 1993 ACM Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems, Malente, Germany, September 1993 and SRC
TECHCON'93, Atlanta, Georgia, September 1993.
409. N. V. Shenoy,
T. G. Szymanski, R. K. Brayton, and A. Sangiovanni-Vincentelli. How Good is the Min-Max Delay Model? In Tau
93: Workshop on Timing Issues in the Specification and Synthesis of Digital
Systems, Sep 1993.
410. N. Shenoy, R. K. Brayton
and A. Sangiovanni-Vincentelli, "Graph Algorithms for Clock Schedule
Optimization. DAC 1993
411. N.V. Shenoy, R.K. Brayton
and A. Sangiovanni-Vincentelli , “Minimum Padding to Satisfy Short Path
Constraints”, Proceedings of the IEEE/ACM International Conference on CAD, pp.
156-161, Santa Clara, CA November 1993.
412. P. McGeer, A. Saldanha,
R. K. Brayton and A. Sangiovanni-Vincentelli, "Delay Models and Exact
Timing Analysis," T. Sasao, editor, Logic Synthesis and Optimization -
Kluwer Academic Publishers, 1993.
413. W. Lam and R. K. Brayton,
"Timed Boolean Functions: Exact Algebraic Timing Analysis," Kluwer
Academic Publishers 1994. Book
414. A. Saldanha, H. Harkness,
P. McGeer, R.K. Brayton and A. Sangiovanni-Vincentelli , “Performance
Optimization Using Exact Sensitization”, Proceedings of the 31st ACM/IEEE Design
Automation Conference, pp. 425- 429, San Diego, CA, June 1994.
415. A. Saldanha, N. Shenoy,
R. K. Brayton, and A. Sangiovanni-Vincentelli, "Functional Clock Schedule
Optimization", The Proceedings of VLSI Design '95 Conference, New Delhi,
India, January 1995, [Best Paper Award].
416. A. Aziz, R. Brayton, F.
Balarin, V. Singhal, "Timing-safe Replaceability for Combinational
Designs", Digest of Papars, TAU'95, Nov. 1995.
417. Z. Li, Y. Zhao, Y. Min,
and Robert K. Brayton, "Timed Binary Decision Diagrams," Design Automation
Conference and International Test Conference, 1997
418. Y. Kukimoto, W. Gosti, A.
Saldanha, R. Brayton, "Approximate Timing Analysis Under the XBD0
Model" International Workshop on Logic Synthesis (IWLS), May 1997.
419. S. Taşıran, Y.
Kukimoto, R. K. Brayton, “Computing Delay with Coupling Using Timed Automata”,
Proc. of IEEE/ACM Intl. Workshop on Timing Issues in the Specification and
Synthesis of Digital Systems, TAU '97, Austin, TX, 1997.
420. Y. Kukimoto, R. Brayton,
"Hierarchical Timing analysis Under the XBD0 Model" International
Workshop on Logic Synthesis (IWLS), May 1997.
421. E. Goldberg, Y. Kukimoto,
R. Brayton, "Canonical TBDDs and Their Application to Combinational
Verification" International Workshop on Logic Synthesis (IWLS), May 1997.
422. Y. Kukimoto and R.
Brayton, "Temporal Flexibility in Combinational Circuits", DAC, June
1997.
423. Y. Kukimoto and R.
Brayton ,"Hierarchical Timing analysis under the XBD0 Model", ICCAD,
Nov. 1997
424. Y. Kukimoto, W. Gosti, A. Saldanha, R. Brayton, Approximate Timing Analysis of
Combinational Circuits Under the XBD0 Model, IEEE/ACM International
Conference on CAD, ICCAD 97, pp. 176-181, November 1997.
425. Y. Kukimoto, R. K. Brayton, Exact Required Time
Analysis via False Path Detection, Proceedings of 34th Design Automation
Conference (DAC97), P220-225, June 1997.
426. Y. Kukimoto, R. K. Brayton, Hierarchical Timing
Analysis under the {XBD0} Model, International Workshop on Logic Synthesis
(IWLS97),
427. Y. Kukimoto, R. K. Brayton, Removing False Paths
from Combinational Modules, Proceedings of TAU97: ACM/IEEE International
Workshop on Timing Issues in the Specification and Synthesis of Digital
Systems, p153-157, Dec 1997.
428. Y. Kukimoto, R. K. Brayton, Delay Characterization
of Combinational Modules, International Workshop on Logic Synthesis (IWLS),
Tahoe City, CA Workshop Notes Volume 2, 446-451, June 1998.
429. Y. Kukimoto, R. Brayton, P. Sawkar,
Delay-Optimal Technology Mapping by DAG Covering, Proceedings of the 35th
Design Automation Conference (DAC 98), pp.348-351, San Francisco, CA, June
1998.
430. Y. Kukimoto, R. Brayton, Hierarchical Functional
Timing Analysis, Proceedings of the 35th Design Automation
Conference (DAC 98), pp. 580-585, San Francisco, CA, June 1998.
431. Y. Kukimoto, R. K. Brayton, Delay Characterization
of Combinational Modules by Functional Arrival Time Analysis, proceedings
of TAU99: ACM/IEEE International Workshop on Timing Issues in the Specification
and Synthesis of Digital Systems, Mar 1999.
432. Y. Kukimoto, R. Brayton, Timing-Safe False Path
Removal for Combinational Modules, IEEE/ACM International Conference on
CAD, ICCAD 99, pp. 544-549, November 1999.