 | minimum feature size (transistor length): 0.35mm |
| 2 polysilicon layers (process option) |
| 4 metal layers |
| n-well (p-type substrate) |
| voltage rating: 3.5V maximum (VDS and VGS). |
Technology Characteristics:
minimum feature size (transistor length): 0.35mm 2 polysilicon layers (process option) 4 metal layers n-well (p-type substrate) voltage rating: 3.5V maximum (VDS and VGS).
SPICE library:
| HSPICE Use only one of nominal/slow/fast per deck! E.g. lib 'cmos35.txt' nominal lib 'cmos35.txt' passive loads the nominal device parameters. To load the fast parameters, replace nominal with fast. |
| Spectre |
| Check your manual if you are using a different version of SPICE for information on how to adapt the technology file. Differences are common e.g. in the parameters describing (flicker) noise and extrinsic capacitances. |
| Model Name | Description |
| nmos | nmos transistor, e.g. mn d g s b nmos l=0.35um w=10um as=10p ad=10p ps=12um pd=12um |
| pmos | pmos transistor mp d g s b pmos l=0.35um w=10um as=10p ad=10p ps=12um pd=12um |
| dwell (capacitor model) | well-to-substrate diode (PMOS) d1 substrate well dwell l=20um w=40um |
| vpnp (pnp model) | parasitic vertical pnp q1 c b e vpnp |
| cpoly (subckt) (see below) |
double poly cap with parasitics x1 top bot topgnd botgnd cpoly c=5pF |
| cm2 (subckt) (see below) |
double metal cap with parasitics x2 top bot topgnd botgnd cm2 c=5pF |
| cm4 (subckt) (see below) |
4 level metal cap with parasitics x3 top bot topgnd botgnd cm4 c=5pF |
Three capacitor versions are available and packaged as subcircuits that include top and bottom plate parasitics. Typically a well underneath the capacitor shields it from noise coupling from the substrate. In this case connect nodes topgnd and botgnd to that shield. Note that the bottom plate often adds substantial loading. Ideal SPICE capacitors should therefore be used only for experimentation and replaced by one of the subcircuits below in a final design.
Page Last Modified on August 14, 2002